Statistical optimization of FinFET processor architectures under PVT variations using dual device-type assignment
With semiconductor technology scaling to the 22nm node and beyond, fin field-effect
transistor (FinFET) has started replacing complementary metal-oxide semiconductor …
transistor (FinFET) has started replacing complementary metal-oxide semiconductor …
Heterogeneous Monolithic 3D and FinFET Architectures for Energy-efficient Computing
Y Yu - 2019 - search.proquest.com
More transistors are integrated within the same footprint area as the technology node
shrinks to deliver higher performance. However, this is accompanied by higher power …
shrinks to deliver higher performance. However, this is accompanied by higher power …
Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits
B Ghavami - COMPEL-The international journal for computation and …, 2018 - emerald.com
Purpose Power consumption is a top priority in high-performance asynchronous circuit
design today. The purpose of this study is to provide a spatial correlation-aware statistical …
design today. The purpose of this study is to provide a spatial correlation-aware statistical …