Efficient bus based router for NOC architecture

A Shrivastava, SK Sharma - World Journal of Engineering, 2016 - emerald.com
Purpose Increase in the speed of processors has led to crucial role of communication in the
performance of systems. As a result, routing is taken into consideration as one of the most …

Fault tolerant architectures for on-chip networks

K Aisopos - 2012 - search.proquest.com
Technology scaling has reached miniaturization levels, where multiple processor cores can
be integrated onto the same die. During the last four decades, this scaling has been the …

Improving the performance of deadlock recovery based routing in irregular mesh NoCs using added mesh-like links

M Hosseingholi, AS Ahmadian… - … Symposium on Circuits …, 2010 - ieeexplore.ieee.org
Heterogeneity is one of the challenges in the current NoC design which forces designers to
consider irregular topologies. Therefore, finding an optimal topology with minimum cost …

Deadlock recovery technique in bus enhanced NOC architecture

SS Nia, A Vafaei, H Shahimohamadi - arXiv preprint arXiv:1209.3564, 2012 - arxiv.org
Increase in the speed of processors has led to crucial role of communication in the
performance of systems. As a result, routing is taken into consideration as one of the most …

Optimizing of deadlock detection methods in routing of multicomputer networks by fuzzy here techniques

M Poornajaf - Fundamental Research in Electrical Engineering: The …, 2019 - Springer
One of the most important issues in parallel processing is routing message from a source
node to destination that is done by routing nodes. Deadlock in routing is a damaging …

[PDF][PDF] An Asynchronous, Low Power and Secure Framework for Network-On-Chips

M Mirza-Aghatabar, A Sadeghi - International Journal of Computer …, 2008 - Citeseer
Summary Network-on-Chip (NoC) is an approach to handle huge number of transistors by
virtue of technology scaling to lower than 50nm. The issue of security has been always …

A double-layer sparse honeycomb topology for NoC

R Gao, F Liu, H Gu, X Fu - Proceedings of 2013 3rd …, 2013 - ieeexplore.ieee.org
Network-on-chip (NoC) is emerging as an effective architecture which address the
shortcomings of traditional bus-based System-on-chip (SoC). Since its better properties …

Deadlock Detection in Routing of Interconnection Networks Using Blocked Channel Fuzzy Method and Traffic Average in Input and Output Channels

M Poornajaf - Fundamental Research in Electrical Engineering: The …, 2019 - Springer
One of the most important issues in parallel processing is routing message from a source
node to destination that is done by routing nodes. Deadlock in routing is a damaging factor …

[PDF][PDF] Deadlock Recovery Technique in Bus Enhanced NOC Architecture

B YUGANDHAR, B MANASA, KVV PRASAD - 2013 - ijvdcs.org
Multiprocessor system on chip is emerging as a new trend for System on chip design but the
wire and power design constraints are forcing adoption of new design methodologies …

Energy analysis of re-injection based deadlock recovery routing algorithms

H Kooti, M Mirza-Aghatabar, S Hessabi… - … on System-on-Chip, 2008 - ieeexplore.ieee.org
There are two strategies for deadlock handling in routing algorithms in NoC: deadlock
avoidance and deadlock recovery. Some deadlock recovery routing algorithms are re …