Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse

MB Taylor - Proceedings of the 49th annual design automation …, 2012 - dl.acm.org
Due to the breakdown of Dennardian scaling, the percentage of a silicon chip that can
switch at full frequency is dropping exponentially with each process generation. This …

A landscape of the new dark silicon design regime

MB Taylor - IEEE Micro, 2013 - ieeexplore.ieee.org
Because of the breakdown of Dennard scaling, the percentage of a silicon chip that can
switch at full frequency drops exponentially with each process generation. This utilization …

Asic clouds: Specializing the datacenter

I Magaki, M Khazraee, LV Gutierrez… - ACM SIGARCH Computer …, 2016 - dl.acm.org
GPU and FPGA-based clouds have already demonstrated the promise of accelerating
computing-intensive workloads with greatly improved power and performance. In this paper …

Cherry-picking: Exploiting process variations in dark-silicon homogeneous chip multi-processors

B Raghunathan, Y Turakhia, S Garg… - … Design, Automation & …, 2013 - ieeexplore.ieee.org
It is projected that increasing on-chip integration with technology scaling will lead to the so-
called dark silicon era in which more transistors are available on a chip than can be …

QsCores: Trading dark silicon for scalable energy efficiency with quasi-specific cores

G Venkatesh, J Sampson, N Goulding-Hotta… - Proceedings of the 44th …, 2011 - dl.acm.org
Transistor density continues to increase exponentially, but power dissipation per transistor is
improving only slightly with each generation of Moore's law. Given the constant chip-level …

Jigsaw: Scalable software-defined caches

N Beckmann, D Sanchez - Proceedings of the 22nd …, 2013 - ieeexplore.ieee.org
Shared last-level caches, widely used in chip-multi-processors (CMPs), face two
fundamental limitations. First, the latency and energy of shared caches degrade as the …

Moonwalk: Nre optimization in asic clouds

M Khazraee, L Zhang, L Vega, MB Taylor - ACM SIGARCH Computer …, 2017 - dl.acm.org
Cloud services are becoming increasingly globalized and data-center workloads are
expanding exponentially. GPU and FPGA-based clouds have illustrated improvements in …

Basejump STL: Systemverilog needs a standard template library for hardware design

MB Taylor - Proceedings of the 55th Annual Design Automation …, 2018 - dl.acm.org
We propose a Standard Template Library (STL) for synthesizeable SystemVerilog that
sharply reduces the time required to design digital circuits. We overview the principles that …

Hades: Architectural synthesis for heterogeneous dark silicon chip multi-processors

Y Turakhia, B Raghunathan, S Garg… - Proceedings of the 50th …, 2013 - dl.acm.org
In this paper, we propose an efficient iterative optimization based approach for architectural
synthesis of dark silicon heterogeneous chip multi-processors (CMPs). The goal is to …

Kismet: parallel speedup estimates for serial programs

D Jeon, S Garcia, C Louie, MB Taylor - Proceedings of the 2011 ACM …, 2011 - dl.acm.org
Software engineers now face the difficult task of refactoring serial programs for parallel
execution on multicore processors. Currently, they are offered little guidance as to how much …