Nanometre-scale electronics with III–V compound semiconductors

JA Del Alamo - Nature, 2011 - nature.com
For 50 years the exponential rise in the power of electronics has been fuelled by an increase
in the density of silicon complementary metal–oxide–semiconductor (CMOS) transistors and …

Atomic layer deposition: an overview

SM George - Chemical reviews, 2010 - ACS Publications
Atomic Layer Deposition: An Overview | Chemical Reviews ACS ACS Publications C&EN CAS
Find my institution Log In Chemical Reviews ACS Publications. Most Trusted. Most Cited. Most …

Considerations for ultimate CMOS scaling

KJ Kuhn - IEEE transactions on Electron Devices, 2012 - ieeexplore.ieee.org
This review paper explores considerations for ultimate CMOS transistor scaling. Transistor
architectures such as extremely thin silicon-on-insulator and FinFET (and related …

Atomic layer deposition of metal oxides and chalcogenides for high performance transistors

C Shen, Z Yin, F Collins, N Pinna - Advanced Science, 2022 - Wiley Online Library
Atomic layer deposition (ALD) is a deposition technique well‐suited to produce high‐quality
thin film materials at the nanoscale for applications in transistors. This review …

Development of hafnium based high-k materials—A review

JH Choi, Y Mao, JP Chang - Materials Science and Engineering: R: Reports, 2011 - Elsevier
The move to implement metal oxide based gate dielectrics in a metal-oxide-semiconductor
field effect transistor is considered one of the most dramatic advances in materials science …

Applications of atomic layer deposition to nanofabrication and emerging nanodevices

H Kim, WJ Maeng - Thin solid films, 2009 - Elsevier
Recently, with scaling down of semiconductor devices, need for nanotechnology has
increased enormously. For nanoscale devices especially, each of the layers should be as …

Band offsets of high K gate oxides on III-V semiconductors

J Robertson, B Falabretti - Journal of applied physics, 2006 - pubs.aip.org
III-V semiconductors have high mobility and will be used in field effect transistors with the
appropriate gate dielectric. The dielectrics must have band offsets over 1 eV to inhibit …

[图书][B] Fundamentals of tunnel field-effect transistors

S Saurabh, MJ Kumar - 2016 - taylorfrancis.com
During the last decade, there has been a great deal of interest in TFETs. To the best authors'
knowledge, no book on TFETs currently exists. The proposed book provides readers with …

Insulated gate and surface passivation structures for GaN-based power transistors

Z Yatabe, JT Asubar, T Hashizume - Journal of Physics D …, 2016 - iopscience.iop.org
Recent years have witnessed GaN-based devices delivering their promise of
unprecedented power and frequency levels and demonstrating their capability as an able …

III–V compound semiconductor transistors—from planar to nanowire structures

H Riel, LE Wernersson, M Hong, JA Del Alamo - Mrs Bulletin, 2014 - cambridge.org
Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic
device roadmap to further improve future performance increases of integrated circuits is …