[图书][B] Analog-to-digital conversion
MJM Pelgrom, MJM Pelgrom - 2013 - Springer
Several classifications exist of Nyquist-rate analog-to-digital converters. In this chapter the
converters are subdivided in parallel search, sequential search, and linear search. Each of …
converters are subdivided in parallel search, sequential search, and linear search. Each of …
ReRAM-based processing-in-memory architecture for recurrent neural network acceleration
We present a recurrent neural network (RNN) accelerator design with resistive random-
access memory (ReRAM)-based processing-in-memory (PIM) architecture. Distinguished …
access memory (ReRAM)-based processing-in-memory (PIM) architecture. Distinguished …
Column-parallel ADCs for CMOS image sensors and their FoM-based evaluations
S Kawahito - IEICE Transactions on Electronics, 2018 - search.ieice.org
This paper reviews architectures and topologies for column-parallel analog-to-digital
converters (ADCs) used for CMOS image sensors (CISs) and discusses the performance of …
converters (ADCs) used for CMOS image sensors (CISs) and discusses the performance of …
A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel ADC Architecture
Y Chae, J Cheon, S Lim, M Kwon, K Yoo… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
This paper presents a 2.1 M pixel, 120 frame/s CMOS image sensor with column-parallel
delta-sigma (ΔΣ) ADC architecture. The use of a second-order ΔΣ ADC improves the …
delta-sigma (ΔΣ) ADC architecture. The use of a second-order ΔΣ ADC improves the …
11-bit column-parallel single-slope ADC with first-step half-reference ramping scheme for high-speed CMOS image sensors
HJ Kim - IEEE Journal of Solid-State Circuits, 2021 - ieeexplore.ieee.org
A first-step half-reference ramping (FHR) readout scheme is presented in this study for high
frame rate CMOS image sensors (CISs). The proposed readout scheme enhances the …
frame rate CMOS image sensors (CISs). The proposed readout scheme enhances the …
A high-speed CMOS image sensor with column-parallel two-step single-slope ADCs
This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed
CMOS image sensors. Error correction scheme to improve the linearity is proposed as well …
CMOS image sensors. Error correction scheme to improve the linearity is proposed as well …
8.9-megapixel video image sensor with 14-b column-parallel SA-ADC
An 8.9-megapixel 60-frames/s video image sensor with a 14-b column-parallel analog-to-
digital converter (ADC) has been developed. A gain amplifier, a 14-b successive …
digital converter (ADC) has been developed. A gain amplifier, a 14-b successive …
An MRAM-based deep in-memory architecture for deep neural networks
This paper presents an MRAM-based deep in-memory architecture (MRAM-DIMA) to
efficiently implement multi-bit matrix vector multiplication for deep neural networks using a …
efficiently implement multi-bit matrix vector multiplication for deep neural networks using a …
2μs row time 12-bit column-parallel single slope ADC for high-speed CMOS image sensor
To improve the conversion speed of single-slope (SS) analog-to-digital converter (ADC) for
high frame rate CMOS image sensor, a cycle time-to-digital converter (TDC)-based readout …
high frame rate CMOS image sensor, a cycle time-to-digital converter (TDC)-based readout …
A 12-bit two-step single-slope ADC with a constant input-common-mode level resistor ramp generator
Q Zhang, N Ning, Z Zhang, J Li, K Wu… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This article presents a 12-bit column-parallel two-step single-slope analog-to-digital
converter (SS ADC). With the merging of analog memory capacitor and input sampling …
converter (SS ADC). With the merging of analog memory capacitor and input sampling …