nvramdisk: A Transactional Block Device Driver for Non-Volatile RAM

J Jung, Y Won - IEEE Transactions on Computers, 2015 - ieeexplore.ieee.org
In this work, we developed nvramdisk, a transactional block device driver for byte-
addressable NVRAM. nvramdisk effectively addresses the key technical challenges in using …

Craft: Criticality-aware fault-tolerance enhancement techniques for emerging memories-based deep neural networks

TH Nguyen, M Imran, J Choi… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Deep neural networks (DNNs) have emerged as the most effective programming paradigm
for computer vision and natural language processing applications. With the rapid …

Low-cost and effective fault-tolerance enhancement techniques for emerging memories-based deep neural networks

TH Nguyen, M Imran, J Choi… - 2021 58th ACM/IEEE …, 2021 - ieeexplore.ieee.org
Deep Neural Networks (DNNs) have been found to outperform conventional programming
approaches in several applications such as computer vision and natural language …

ECS: Error-correcting strings for lifetime improvements in nonvolatile memories

S Swami, PM Palangappa, K Mohanram - ACM Transactions on …, 2017 - dl.acm.org
Emerging nonvolatile memories (NVMs) suffer from low write endurance, resulting in early
cell failures (hard errors), which reduce memory lifetime. It was recognized early on that …

Yoda: Judge me by my size, do you?

J Zhang, D Kline, L Fang, R Melhem… - … on Computer Design …, 2017 - ieeexplore.ieee.org
Phase change memory is a promising alternative to conventional memories such as DRAM
due to its density and non-volatility. Unfortunately, reliability is still a challenge as limited …

Locally rewritable codes for resistive memories

Y Kim, AA Sharma, R Mateescu… - IEEE Journal on …, 2016 - ieeexplore.ieee.org
Resistive memories, such as phase change memories and resistive random access
memories, have attracted significant research interest because of their scalability, non …

Reset-check-reverse-flag scheme on NRAM with 50% bit error rate or 35% parity overhead and 16% decoding latency reductions for read-intensive storage class …

S Ning, TO Iwasaki, S Tanakamaru… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
A novel error correction scheme, called reset-checkreverse-flag (RCRF), is proposed to
improve the reliability of storage class memories (SCMs). RCRF divides the conventional …

Multi-step pre-read for write operations in memory devices

YC Lee, NN Gajera, K Sarpatwari - US Patent 12,106,803, 2024 - Google Patents
Abstract Systems, methods, and apparatus related to memory devices. In one approach, a
memory device has a memory array including memory cells. A controller of the memory …

Performance of BCH and RS Codes in MIMO System Using MPFEC Diversity Technique

AB Al-Khalil, A Al-Barrak - 2018 International Conference on …, 2018 - ieeexplore.ieee.org
Multipath propagation phenomenon often causes Inter-Symbol Interference (ISI) because
several copies from the originally transmitted signal travel in different directions and reach …

Mitigating stuck cell failures in MLC NAND flash memory via inferred erasure decoding

AA Chaudhry, C Kui, YL Guan - IEEE Transactions on Very …, 2017 - ieeexplore.ieee.org
The multilevel-cell NAND flash memory experiences permanent hard errors due to cell
defects (stuck cells). To overcome this problem, stuck cells are either regarded as erasures …