A programmable processor and method for improving the performance of processors by
expanding at least two source operands, or a source and a result operand, to a width greater …

Methods and apparatus for encoding codewords which are particularly well Suited for use
with low density parity check (LDPC) codes and long codewords are described. The …

(57) ABSTRACT A flexible and relatively hardware efficient LDPC encoder is described. The
encoder can be implemented with a level of parallelism which is less than the full parallelism …

First worldwide family litigation filed litigation Critical https://patents. darts-ip. com/? family=
40526635&utm_source= google_patent&utm_medium= platform_link&utm_campaign …

A programmable processor and method for improving the performance of processors by
expanding at least two source operands, or a source and a result operand, to a width greater …

Methods and apparatus for decoding codewords using mes sage passing decoding
techniques which are particularly well suited for use with low density parity check (LDPC) …

Techniques for implementing message passing decoders, eg, LDPC decoders, are
described. To facilitate hardware implementation messages are quantized to integer …

An iterative message passing decoder, eg, an LDPC decoder, operating in conjunction with
a soft input-soft output signal processing unit, eg, an ISI detector, has an error floor …

First worldwide family litigation filed litigation https://patents. darts-ip. com/? family=
29273786&utm_source= google_patent&utm_medium= platform_link&utm_campaign …

Generating mixed-mode operations in the compilation of program code for processors
having vector or SIMD processing units is disclosed. In a preferred embodiment of the …