Reliable ultra-low-voltage cache design for many-core systems

M Zhang, VM Stojanovic… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
We reduce cache supply voltage below the normally acceptable VDDMIN, in order to
improve overall many-core system energy efficiency. Based on the observation that cache …

Leveraging on deep memory hierarchies to minimize energy consumption and data access latency on single-chip cloud computers

T Maqsood, N Tziritas, T Loukopoulos… - IEEE Transactions …, 2017 - ieeexplore.ieee.org
Recent advances in chip design and integration technologies have led to the development
of Single-Chip Cloud computers which are a microcosm of cloud datacenters. Those …

A Fault-Tolerant L1 Cache with Predictable Performance by Virtual Filter Cache

H Zhi-Bin, M Hua-Dong, Z Feng… - 2016 13th International …, 2016 - ieeexplore.ieee.org
The Subblock-Disabling schemes have obviousadvantages on delays overhead and
capacity loss. However, theexistence of cache line" holes" triggers abundant false hits …

[PDF][PDF] Energy-Efficient Task and Data Scheduling for Large-Scale Computing Systems

T Maqsood - 2016 - academia.edu
With the recent advancements in integration technologies and aggressive transistor scaling,
dozens or even hundreds of processing cores can be integrated onto a single chip changing …

[图书][B] Resilient On-Chip Memory Design in the Nano Era

A BanaiyanMofrad - 2015 - search.proquest.com
Aggressive technology scaling in the nano-scale regime makes chips more susceptible to
failures. This causes multiple reliability challenges in the design of modern chips, including …

[PDF][PDF] A Complete Bibliography of ACM Transactions on Embedded Computing Systems (TECS)

NHF Beebe - 2024 - ctan.math.utah.edu
[BCHL19, BCEP12, BM13, CP13a, CDBB24, CKGN14, CC14, CBH22a, CBH22b, CP13b,
DV13, DSD12, Edi13, FM12, GV21b, Goe14, GP07, HCK+08, HTLC10, Hüb13, JB02, JB03 …