Power, thermal, and reliability modeling in nanometer-scale microprocessors

D Brooks, RP Dick, R Joseph, L Shang - Ieee Micro, 2007 - ieeexplore.ieee.org
System integration and performance requirements are dramatically increasing the power
consumptions and power densities of high-performance microprocessors. High power …

Using dependence analysis to support the software maintenance process

JP Loyall, SA Mathisen - 1993 Conference on Software …, 1993 - ieeexplore.ieee.org
Dependence analysis is useful for software maintenance because it indicates the possible
effects of a software modification on the rest of a program. This helps the software maintainer …

Apparatus, method and program product for adaptive real-time power and perfomance optimization of multi-core processors

D Kim, J Kim, MJ Kim, JR Moulic - US Patent 8,578,193, 2013 - Google Patents
An apparatus, method and program product for optimizing core performance and power in of
a multi-core processor. The apparatus includes a multi-core processor coupled to a clock …

Scheduling threads on different processor cores based on memory temperature

G Memik, SO Memik, B Mangione-Smith - US Patent 8,819,686, 2014 - Google Patents
Techniques for scheduling a thread running in a computer system are disclosed. Example
computer systems may include but are not limited to a multiprocessor having first and …

Redundancy mining for soft error detection in multicore processors

R Hyman, K Bhattacharya… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
The trends in technology scaling and the reduction in supply voltages have significantly
improved the performance and energy consumption in modern microprocessors …

Core selection for applications running on multiprocessor systems based on core and application characteristics

G Memik, SO Memik, B Mangione-Smith - US Patent 8,924,975, 2014 - Google Patents
7,954, 101 B2 5/2011 Adachi et al. 8,122,187 B2 2/2012 Walker et al. 8,161,304 B2 4/2012
Hamilton 2002fO112097 A1 2004/O193778 A1 2004/O19973O A1 2005/O12O252 A1 …

Power supply noise aware workload assignment for multi-core systems

A Todri, M Marek-Sadowska… - 2008 IEEE/ACM …, 2008 - ieeexplore.ieee.org
As the industry moves from single-to multicore processors, the challenges of how to reliably
design and analyze power delivery for such systems also arise. We study various workload …

An energy-efficient directory based multicore architecture with wireless routers to minimize the communication latency

A Asaduzzaman, KK Chidella… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
Multicore architectures suffer from high core-to-core communication latency primarily due to
the cache's dynamic behavior. Studies suggest that a directory-approach can be helpful to …

Scheduling of threads by batch scheduling

G Memik, SO Memik, B Mangione-Smith - US Patent 8,839,255, 2014 - Google Patents
US8839255B2 - Scheduling of threads by batch scheduling - Google Patents US8839255B2 -
Scheduling of threads by batch scheduling - Google Patents Scheduling of threads by batch …

UnSync-CMP: Multicore CMP architecture for energy-efficient soft-error reliability

R Jeyapaul, F Hong, A Rhisheekesan… - … on Parallel and …, 2013 - ieeexplore.ieee.org
Reducing device dimensions, increasing transistor densities, and smaller timing windows,
expose the vulnerability of processors to soft errors induced by charge carrying particles …