Ultra-low power VLSI circuit design demystified and explained: A tutorial
M Alioto - IEEE Transactions on Circuits and Systems I: Regular …, 2012 - ieeexplore.ieee.org
In this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a
unitary framework for the first time. A few general principles are first introduced to gain an …
unitary framework for the first time. A few general principles are first introduced to gain an …
Mafia: A maximal frequent itemset algorithm for transactional databases
We present a new algorithm for mining maximal frequent itemsets from a transactional
database. Our algorithm is especially efficient when the itemsets in the database are very …
database. Our algorithm is especially efficient when the itemsets in the database are very …
[图书][B] FinFET modeling for IC simulation and design: using the BSIM-CMG standard
This book is the first to explain FinFET modeling for IC simulation and the industry standard–
BSIM-CMG-describing the rush in demand for advancing the technology from planar to 3D …
BSIM-CMG-describing the rush in demand for advancing the technology from planar to 3D …
A low-voltage low-power voltage reference based on subthreshold MOSFETs
G Giustolisi, G Palumbo, M Criscione… - IEEE Journal of Solid …, 2003 - ieeexplore.ieee.org
In this work, a new low-voltage low-power CMOS voltage reference independent of
temperature is presented. It is based on subthreshold MOSFETs and on compensating a …
temperature is presented. It is based on subthreshold MOSFETs and on compensating a …
Tunneling field-effect transistor: capacitance components and modeling
Y Yang, X Tong, LT Yang, PF Guo… - IEEE Electron Device …, 2010 - ieeexplore.ieee.org
We report a numerical simulation study of gate capacitance components in a tunneling field-
effect transistor (TFET), showing key differences in the partitioning of gate capacitance …
effect transistor (TFET), showing key differences in the partitioning of gate capacitance …
Analyses of static and dynamic random offset voltages in dynamic comparators
J He, S Zhan, D Chen, RL Geiger - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
When mismatches are present in a dynamic comparator, due to internal positive feedback
and transient response, it is always challenging to analytically predict the input-referred …
and transient response, it is always challenging to analytically predict the input-referred …
An ultra-low-voltage ultra-low-power CMOS Miller OTA with rail-to-rail input/output swing
LHC Ferreira, TC Pimenta… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
An ultra-low-voltage ultra-low-power CMOS Miller operational transconductance amplifier
(OTA) with rail-to-rail input/output swing is presented. The topology is based on combining …
(OTA) with rail-to-rail input/output swing is presented. The topology is based on combining …
A 12-bit 10 MS/s SAR ADC with high linearity and energy-efficient switching
S Liu, Y Shen, Z Zhu - … Transactions on Circuits and Systems I …, 2016 - ieeexplore.ieee.org
A 12-bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this
paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and …
paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and …
Compact modeling
G Gildenblat - Netherlands: Springer, 2010 - Springer
Models of circuit elements which are sufficiently simple to be incorporated in circuit
simulators and are sufficiently accurate to make the outcome useful to circuit designers are …
simulators and are sufficiently accurate to make the outcome useful to circuit designers are …
BSIM—SPICE models enable FinFET and UTB IC designs
Two turn-key surface potential-based compact models are developed to simulate multigate
transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is …
transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is …