Epitaxial substitution of metal iodides for low-temperature growth of two-dimensional metal chalcogenides
The integration of various two-dimensional (2D) materials on wafers enables a more-than-
Moore approach for enriching the functionalities of devices,–. On the other hand, the additive …
Moore approach for enriching the functionalities of devices,–. On the other hand, the additive …
[HTML][HTML] All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration
Abstract 3D monolithic integration of logic and memory has been the most sought after
solution to surpass the Von Neumann bottleneck, for which a low-temperature processed …
solution to surpass the Von Neumann bottleneck, for which a low-temperature processed …
[HTML][HTML] Heterogeneous and monolithic 3D integration technology for mixed-signal ICs
For next-generation system-on-chips (SoCs) in diverse applications (RF, sensor, display,
etc.) which require high-performance, small form factors, and low power consumption …
etc.) which require high-performance, small form factors, and low power consumption …
Radiation effects in a post-Moore world
DM Fleetwood - IEEE Transactions on Nuclear Science, 2021 - ieeexplore.ieee.org
An overview is presented of the significant influences of Moore's Law scaling on radiation
effects on microelectronics, focusing on historical trends and future needs. A number of …
effects on microelectronics, focusing on historical trends and future needs. A number of …
Gate-based high fidelity spin readout in a CMOS device
The engineering of a compact qubit unit cell that embeds all quantum functionalities is
mandatory for large-scale integration. In addition, these functionalities should present the …
mandatory for large-scale integration. In addition, these functionalities should present the …
[HTML][HTML] Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review
YJ Jang, A Sharma, JP Jung - Materials, 2023 - mdpi.com
Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for
achieving high-density integration, high-speed connectivity, and for downsizing of electronic …
achieving high-density integration, high-speed connectivity, and for downsizing of electronic …
Atomic layer deposition of large-area polycrystalline transition metal dichalcogenides from 100° C through control of plasma chemistry
Two-dimensional transition metal dichalcogenides, such as MoS2, are intensely studied for
applications in electronics. However, the difficulty of depositing large-area films of sufficient …
applications in electronics. However, the difficulty of depositing large-area films of sufficient …
Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications
A Veloso, T Huynh-Bao, P Matagne, D Jang… - Solid-State …, 2020 - Elsevier
We report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around
(GAA) FET devices as promising candidates to obtain a better power-performance metric for …
(GAA) FET devices as promising candidates to obtain a better power-performance metric for …
[HTML][HTML] Quantum confinement-induced semimetal-to-semiconductor evolution in large-area ultra-thin PtSe2 films grown at 400 °C
In this work, we present a comprehensive theoretical and experimental study of quantum
confinement in layered platinum diselenide (PtSe2) films as a function of film thickness. Our …
confinement in layered platinum diselenide (PtSe2) films as a function of film thickness. Our …
Microsystems using three-dimensional integration and TSV technologies: Fundamentals and applications
Z Wang - Microelectronic Engineering, 2019 - Elsevier
As a powerful enabling technology, three-dimensional (3D) integration, which uses wafer
bonding to integrate multiple wafers in the vertical direction and uses through‑silicon-vias …
bonding to integrate multiple wafers in the vertical direction and uses through‑silicon-vias …