(57) ABSTRACT A processor includes a plurality of processor tiles, each tile including a
processor core, and an interconnection network interconnects the processor cores and …

Abstract Systems and methods described herein are directed to solutions for NoC
interconnects that provide congestion avoidance and end-to-end uniform and weighted-fair …

GO6F 3/40(2006.01) f lan for a N k on Chi C 1 h GO6F 5/78 (2006.01) oor plan for a Network
on Chip (NoC) topology that can include a plurality of on chip blocks of substantially non …

Example implementations described herein are directed to a system on chip (SoC) that can
include a plurality of blocks of substantially non-uniform shapes and dimensions, a plurality …

Abstract Systems and methods described herein are directed to streaming bridge design
implementations that help interconnect and transfer transaction packets between multiple …

(57) ABSTRACT A method to design a Networks on Chips (NoCs)-based com munication
system for connecting on-chip components in a multicore system, said system comprising …

Abstract Systems and methods for automatically building a deadlock free inter-
communication network in a multi-core system are described. The example embodiments …

Abstract Systems and methods involving construction of a system interconnect in which
different channels have different widths in numbers of bits. Example processes to construct …

Aspects of the present disclosure relate to a method and system for hybrid and/or distributed
implementation of generation and/or execution of power profile management instructions …

Addition, search, and performance of other allied activities relating to keys are performed in
a hardware hash table. Further, high performance and efficient design may be pro vided for …