[HTML][HTML] ASAP7: A 7-nm finFET predictive process design kit
We describe a 7-nm predictive process design kit (PDK) called the ASAP7 PDK, developed
in collaboration with ARM Ltd. for academic use. The PDK is realistic, based on current …
in collaboration with ARM Ltd. for academic use. The PDK is realistic, based on current …
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
CH Jan, U Bhattacharya, R Brain… - 2012 International …, 2012 - ieeexplore.ieee.org
A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power
SoC products for the first time. Low standby power and high voltage transistors exploiting the …
SoC products for the first time. Low standby power and high voltage transistors exploiting the …
A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product …
A leading edge 32nm high-k/metal gate transistor technology has been optimized for SoC
platform applications that span a wide range of power, performance, and feature space. This …
platform applications that span a wide range of power, performance, and feature space. This …
World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS
T Naito, T Ishida, T Onoduka… - 2010 Symposium on …, 2010 - ieeexplore.ieee.org
World's first monolithically integrated Thin-Film-Transistor (TFT) SRAM configuration circuits
over 90nm 9 layers of Cu interconnect CMOS is successfully fabricated at 300mm LSI mass …
over 90nm 9 layers of Cu interconnect CMOS is successfully fabricated at 300mm LSI mass …
A 16nm FinFET CMOS technology for mobile SoC and computing applications
SY Wu, CY Lin, MC Chiang, JJ Liaw… - 2013 IEEE …, 2013 - ieeexplore.ieee.org
For the first time, we present a state-of-the-art energy-efficient 16nm technology integrated
with FinFET transistors, 0.07 um 2 high density (HD) SRAM, Cu/low-k interconnect and high …
with FinFET transistors, 0.07 um 2 high density (HD) SRAM, Cu/low-k interconnect and high …
340 mv–1.1 v, 289 gbps/w, 2090-gate nanoaes hardware accelerator with area-optimized encrypt/decrypt gf (2 4) 2 polynomials in 22 nm tri-gate cmos
This paper describes an on-die lightweight nanoAES hardware accelerator, fabricated in 22
nm tri-gate high-k/metal-gate CMOS, targeted for ultra-low power symmetric-key encryption …
nm tri-gate high-k/metal-gate CMOS, targeted for ultra-low power symmetric-key encryption …
Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
K Cheng, A Khakifirooz, P Kulkarni… - 2009 IEEE …, 2009 - ieeexplore.ieee.org
We present a new ETSOI CMOS integration scheme. The new process flow incorporates all
benefits from our previous unipolar work. Only a single mask level is required to form raised …
benefits from our previous unipolar work. Only a single mask level is required to form raised …
A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low …
CH Jan, F Al-Amoody, HY Chang… - 2015 Symposium on …, 2015 - ieeexplore.ieee.org
A leading edge 14 nm SoC platform technology based upon the 2 nd generation Tri-Gate
transistor technology [5] has been optimized for density, low power and wide dynamic range …
transistor technology [5] has been optimized for density, low power and wide dynamic range …
RF CMOS technology scaling in high-k/metal gate era for RF SoC (system-on-chip) applications
CH Jan, M Agostinelli, H Deshpande… - 2010 international …, 2010 - ieeexplore.ieee.org
The impact of silicon technology scaling trends and the associated technological
innovations on RF CMOS device characteristics are examined. The application of novel …
innovations on RF CMOS device characteristics are examined. The application of novel …
High-k/metal gate innovations enabling continued CMOS scaling
MM Frank - 2011 Proceedings of the European Solid-State …, 2011 - ieeexplore.ieee.org
High-k dielectrics and metal gate electrodes have entered complementary metal-oxide-
semiconductor (CMOS) logic technology, integrated in both gate-first and gate-last schemes …
semiconductor (CMOS) logic technology, integrated in both gate-first and gate-last schemes …