Hypersnn: A new efficient and robust deep learning model for resource constrained control applications

Z Yan, S Wang, K Tang, WF Wong - arXiv preprint arXiv:2308.08222, 2023 - arxiv.org
In light of the increasing adoption of edge computing in areas such as intelligent furniture,
robotics, and smart homes, this paper introduces HyperSNN, an innovative method for …

Design and analysis of linear feedback shift register (LFSR) using gate diffusion input (GDI) technique

R Sharma, B Singh - 2016 5th International Conference on …, 2016 - ieeexplore.ieee.org
In chip manufacturing technology, reduction in chip size possess great concern for power
dissipation. Low power testing has become an important issue as power dissipation during …

[PDF][PDF] In-Depth Survey on XOR Gate Design

M Babu, SK GA - IN-DEPTH, 2020 - researchgate.net
XOR gate has a very important role in most of the cryptographic algorithms. Because of
anticoincident property, the XOR gate can be used as a Cipher and the same architecture …

Optimized low power full adder design

V Thenmozhi, R Muthaiah - 2017 International Conference on …, 2017 - ieeexplore.ieee.org
This paper, proposed a hybrid full adder with low power and less area using 8 transistors.
Majority not gate and GDI techniques are collectively used for design this hybrid full adder …

[PDF][PDF] Design of Faster SMS4 Crypto System with Efficient XOR Gate

M Babu, GA Sathishkumar - IJAST, 2020 - researchgate.net
In this internet era, the security of data over a wireless medium is the biggest challenge. And
the faster processing and transmission of data also a big challenge in areas like defense …

[PDF][PDF] Performance analysis of quantum dot cellular automata (QCA) based linear feedback shift register (LFSR)

BS Kalyan, B Singh - … Journal of Computing and Digital Systems, 2020 - researchgate.net
The latest trends in the digital design circuits are based on Quantum Dot based structures.
The Quantum-dot Cellular automata is paradigm in the area of Nano chip design in terms of …

High-performance low-power 5: 2 compressor with 30 CNTFETs using 32 nm technology

JK Saini, A Srinivasulu… - International Journal of …, 2019 - ingentaconnect.com
Background: The advent of High Performance Computing (HPC) applications and big data
applications has made it imparitive to develop hardware that can match the computing …

The complexity of finding medians

S Toda - Proceedings [1990] 31st Annual Symposium on …, 1990 - ieeexplore.ieee.org
PF (Hash P) is characterized in a manner similar to MW Krentel's (1988) characterization of
Pf (NP). If MidP is the class of functions that give the medians in the outputs of metric Turing …

A 0.8V 0.23nW 1.5ns Full‐Swing Pass‐Transistor XOR Gate in 130nm CMOS

N Ahmad, R Hasan - Active and Passive Electronic …, 2013 - Wiley Online Library
A power efficient circuit topology is proposed to implement a low‐voltage CMOS 2‐input
pass‐transistor XOR gate. This design aims to minimize power dissipation and reduce …

FPGA Implementation Of A Modified SMS4-BSK Cipher With Novel Efficient Xor Gate Design

M Babu, GAS Kumar, K Sivachandar… - 2022 7th …, 2022 - ieeexplore.ieee.org
The SMS4-BSK cipher is a secure encryption algorithm that prevents data packets' security
threats over the wireless medium. In this paper, the novel design of a 4Transistor XOR gate …