parSC: Synchronous parallel SystemC simulation on multi-core host architectures
C Schumacher, R Leupers, D Petras… - Proceedings of the eighth …, 2010 - dl.acm.org
Time-consuming cycle-accurate MPSoC simulation is often needed for debugging and
verification. Its practicability is put at risk by the growing MPSoC complexity. This work …
verification. Its practicability is put at risk by the growing MPSoC complexity. This work …
Parallelizing SystemC kernel for fast hardware simulation on SMP machines
P Ezudheen, P Chandran, J Chandra… - 2009 ACM/IEEE …, 2009 - ieeexplore.ieee.org
SystemC is a system-level modeling language and simulation framework which facilitates
design and verification of processor designs at different levels. Recently, SystemC is …
design and verification of processor designs at different levels. Recently, SystemC is …
Parallel programming with SystemC for loosely timed models: A non-intrusive approach
M Moy - 2013 Design, Automation & Test in Europe Conference …, 2013 - ieeexplore.ieee.org
The SystemC/TLM technologies are widely accepted in the industry for fast system-level
simulation. An important limitation of SystemC regarding performance is that the reference …
simulation. An important limitation of SystemC regarding performance is that the reference …
Out-of-order parallel discrete event simulation for transaction level models
The validation of system models at the transaction-level typically relies on discrete event
(DE) simulation. In order to reduce simulation time, parallel discrete event simulation (PDES) …
(DE) simulation. In order to reduce simulation time, parallel discrete event simulation (PDES) …
Resource server providing a rapidly changing resource
M Thomas, GD Baulier - US Patent 9,369,406, 2016 - Google Patents
US9369406B2 - Resource server providing a rapidly changing resource - Google Patents
US9369406B2 - Resource server providing a rapidly changing resource - Google Patents …
US9369406B2 - Resource server providing a rapidly changing resource - Google Patents …
Multi-core parallel simulation of system-level description languages
The validation of transaction level models described in System-level Description Languages
(SLDLs) often relies on extensive simulation. However, traditional Discrete Event (DE) …
(SLDLs) often relies on extensive simulation. However, traditional Discrete Event (DE) …
SimParallel: A high performance parallel SystemC simulator using hierarchical multi-threading
MK Chung, JK Kim, S Ryu - 2014 IEEE International …, 2014 - ieeexplore.ieee.org
As the system complexity increases, the simulation performance becomes one of the most
important issues in virtual prototyping. Parallel simulation is a fascinating technique for high …
important issues in virtual prototyping. Parallel simulation is a fascinating technique for high …
Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs
RS Khaligh, M Radetzki - 2010 Design, Automation & Test in …, 2010 - ieeexplore.ieee.org
We present a set of modeling constructs accompanied by a high performance simulation
kernel for accuracy adaptive transaction level models. In contrast to traditional, fixed …
kernel for accuracy adaptive transaction level models. In contrast to traditional, fixed …
Multicore simulation of transaction-level models using the soc environment
Editor's note: To address the limitations of discrete-event simulation engines, this article
presents an extension of the SoC simulation kernel to support parallel simulation on …
presents an extension of the SoC simulation kernel to support parallel simulation on …
Parallel discrete event simulation of transaction level models
Describing Multi-Processor Systems-on-Chip (MPSoC) at the abstract Electronic System
Level (ESL) is one task, validating them efficiently is another. Here, fast and accurate system …
Level (ESL) is one task, validating them efficiently is another. Here, fast and accurate system …