Bbb: Simplifying persistent programming using battery-backed buffers
M Alshboul, P Ramrakhyani, W Wang… - … Symposium on High …, 2021 - ieeexplore.ieee.org
Non-volatile memory (NVM) is poised to augment or replace DRAM as main memory. With
the right abstraction and support, non-volatile main memory (NVMM) can provide an …
the right abstraction and support, non-volatile main memory (NVMM) can provide an …
Persistent processor architecture
This paper presents PPA (Persistent Processor Architecture), simple microarchitectural
support for lightweight yet performant whole-system persistence. PPA offers fully transparent …
support for lightweight yet performant whole-system persistence. PPA offers fully transparent …
A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate
The impact of alpha particle and exposure to cosmic radiation has multifold the existing
stability issue associated with modern sub-100 nm SRAM cell design. Noise insertion in the …
stability issue associated with modern sub-100 nm SRAM cell design. Noise insertion in the …
A low power single bit-line configuration dependent 7T SRAM bit cell with process-variation-tolerant enhanced read performance
Cache memory is a key component for most microprocessors in embedded system. The
increasing processing load has resulted in an upsurge in the demand for low power, high …
increasing processing load has resulted in an upsurge in the demand for low power, high …
Design and comparative analysis of SRAM array using low leakage controlled transistor technique with improved delay
K Gavaskar, MS Narayanan, MS Nachammal… - Journal of Ambient …, 2022 - Springer
Static random access memory power and speed dissipation are the significant factor in most
of the electronic applications, which prompts numerous plans with the power utilization of …
of the electronic applications, which prompts numerous plans with the power utilization of …
A read disturbance free differential read SRAM cell for low power and reliable cache in embedded processor
D Nayak, DP Acharya, K Mahapatra - AEU-International Journal of …, 2017 - Elsevier
Energy consumption and data stability are vital requirement of cache in embedded
processor. SRAM is a natural choice for cache memory owing to their speed and energy …
processor. SRAM is a natural choice for cache memory owing to their speed and energy …
Current starving the SRAM Cell: a strategy to improve cell stability and power
D Nayak, DP Acharya, K Mahapatra - Circuits, Systems, and Signal …, 2017 - Springer
In SRAM cell design, the energy consumption and cell stability are the major performance
indices which need to be improved. Several techniques reported earlier attempt to improve …
indices which need to be improved. Several techniques reported earlier attempt to improve …
A novel charge recycle read write assist technique for energy efficient and fast 20 nm 8T-SRAM array
The read instability of conventional 6T-SRAM cell has made the 8T-SRAM cell a substitute
for high data reliability. But the single ended nature of read operation demands a complete V …
for high data reliability. But the single ended nature of read operation demands a complete V …
SecPB: Architectures for Secure Non-Volatile Memory with Battery-Backed Persist Buffers
The durability of data stored in persistent memory (PM) exposes data to potentially data
leakage attacks. Recent research has identified the requirements for crash recoverable …
leakage attacks. Recent research has identified the requirements for crash recoverable …
Design and implementation of different types of full adders in ALU and leakage minimization
In the era of nanotechnology, leakage current, active power, delay, area bear an important
metric for design and analysis of complex arithmetic logic circuits. In this paper major work …
metric for design and analysis of complex arithmetic logic circuits. In this paper major work …