Efficient dynamic reconfigurable cnn accelerator for edge intelligence computing on fpga
K Shi, M Wang, X Tan, Q Li, T Lei - Information, 2023 - mdpi.com
This paper proposes an efficient dynamic reconfigurable CNN accelerator (EDRCA) for
FPGAs to tackle the issues of limited hardware resources and low energy efficiency in the …
FPGAs to tackle the issues of limited hardware resources and low energy efficiency in the …
The suitability assessment for land territorial spatial planning based on ANN-CA model and the Internet of Things
Z Nie - Heliyon, 2024 - cell.com
This work aims to utilize Internet of Things (IoT) technology and the Artificial Neural Network-
Cellular Automaton (ANN-CA) model to analyze the construction of indicators for territorial …
Cellular Automaton (ANN-CA) model to analyze the construction of indicators for territorial …
Utilizing MRAMs with Low Resistance and Limited Dynamic Range for Efficient MAC Accelerator
K Chakarwar, S Sahay - IEEE Open Journal of …, 2024 - ieeexplore.ieee.org
The recent advancements in data mining, machine learning algorithms and cognitive
systems have necessitated the development of neuromorphic processing engines which …
systems have necessitated the development of neuromorphic processing engines which …
Enhancing Image Segmentation Performance with MRAM based Processing-in-Memory Architecture
Image segmentation is essential for several computer vision applications, including object
detection, autonomous driving, and medical imaging. Traditional image segmentation …
detection, autonomous driving, and medical imaging. Traditional image segmentation …
Dynamic Time-Domain Sensing Scheme for Spin-Orbit Torque MRAM
While spin-orbit torque magnetic random access memory (SOT-MRAM) have shown huge
potential for building next-generation embedded memory due to their attractive …
potential for building next-generation embedded memory due to their attractive …
[PDF][PDF] High-Performance Multi-level Cell Design Using Reduced Retention Time Spintronics Device.
A PB, TS Warrier - Electrica, 2024 - electricajournal.org
Present-day computationally intensive on-chip applications consume much area and
energy. Multi-level cells (MLCs) capable of storing two-bit information can reduce this area …
energy. Multi-level cells (MLCs) capable of storing two-bit information can reduce this area …
[PDF][PDF] High-Performance Multi-level Cell Design Using Reduced Retention Time Spintronics Device
PB Alisha, TS Warrier - 2024 - electricajournal.org
Present-day computationally intensive on-chip applications consume much area and
energy. Multi-level cells (MLCs) capable of storing two-bit information can reduce this area …
energy. Multi-level cells (MLCs) capable of storing two-bit information can reduce this area …