A survey of FPGA-based LDPC decoders
P Hailes, L Xu, RG Maunder… - … Surveys & Tutorials, 2015 - ieeexplore.ieee.org
Low-density parity check (LDPC) error correction decoders have become popular in
communications systems, as a benefit of their strong error correction performance and their …
communications systems, as a benefit of their strong error correction performance and their …
A survey on programmable LDPC decoders
Low-density parity-check (LDPC) block codes are popular forward error correction schemes
due to their capacity-approaching characteristics. However, the realization of LDPC …
due to their capacity-approaching characteristics. However, the realization of LDPC …
Memory system optimization for FPGA-based implementation of quasi-cyclic LDPC codes decoders
Designers are increasingly relying on field-programmable gate array (FPGA)-based
emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically …
emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically …
VLSI design for low-density parity-check code decoding
Low-Density Parity-check (LDPC) code, being one of the most promising near-Shannon limit
error correction codes (ECCs) in practice, has attracted tremendous attention in both …
error correction codes (ECCs) in practice, has attracted tremendous attention in both …
Layered LDPC decoders with efficient memory access scheduling and mapping and built-in support for pipeline hazards mitigation
O Boncalo, G Kolumban-Antal… - … on Circuits and …, 2018 - ieeexplore.ieee.org
This paper proposes a holistic approach that addresses both the message mapping in
memory banks and the pipeline-related data hazards in low-density parity-check (LDPC) …
memory banks and the pipeline-related data hazards in low-density parity-check (LDPC) …
A novel ldpc decoder for dvb-s2 ip
S Muller, M Schreger, M Kabutz, M Alles… - … , Automation & Test …, 2009 - ieeexplore.ieee.org
In this paper a programmable Forward Error Correction (FEC) IP for a DVB-S2 receiver is
presented. It is composed of a Low-Density Parity Check (LDPC), a Bose-Chaudhuri …
presented. It is composed of a Low-Density Parity Check (LDPC), a Bose-Chaudhuri …
Conflict resolution for pipelined layered LDPC decoders
C Marchand, JB Doré… - … IEEE Workshop on …, 2009 - ieeexplore.ieee.org
Many of the current LDPC implementations of DVB-S2, T2 or WiMAX standard use the so-
called layered architecture combined with pipeline. However, the pipeline process may …
called layered architecture combined with pipeline. However, the pipeline process may …
Massive parallel LDPC decoding on GPU
Low-Density Parity-Check (LDPC) codes are powerful error correcting codes (ECC). They
have recently been adopted by several data communication standards such as DVB-S2 and …
have recently been adopted by several data communication standards such as DVB-S2 and …
Architecture and finite precision optimization for layered LDPC decoders
Layered decoding is known to provide efficient and high-throughput implementation of
LDPC decoders. However, two main issues affect performance and area of practical …
LDPC decoders. However, two main issues affect performance and area of practical …
[PDF][PDF] 动态自适应低密度奇偶校验码译码器的FPGA 实现
兰亚柱， 杨海钢， 林郁 - 电子与信息学报, 2015 - edit.jeit.ac.cn
在复杂深空通信环境中, 自适应能力的强弱对低密度奇偶校验(LDPC) 码译码器能否保持长期
稳定工作具有重要影响. 该文通过对DVB-S2 标准LDPC 码译码器各功能模块的IP 化设计 …
稳定工作具有重要影响. 该文通过对DVB-S2 标准LDPC 码译码器各功能模块的IP 化设计 …