In this paper we present a methodology to develop efficient and deadlock free routing
algorithms for Network-on-Chip (NoC) platforms which are specialized for an application or …

We compare the performance of four admission control algorithms-one parameter-based
and three measurement-based-for controlled-load service. The parameter-based admission …

This paper explores, with numerical case studies, the performance of an optimization
algorithm that is a variant of EPSO, the Evolutionary Particle Swarm Optimization method …

Beyond a certain number of cores, multi-core processing chips will require a network-on-
chip (NoC) to interconnect the cores and overcome the limitations of a bus. NoCs must be …

With the rapid development of semiconductor industry, the number of cores integrated on
chip increases quickly, which brings tough challenges such as bandwidth, scalability and …

In this paper, we present a methodology to specialize the routing algorithm in routing table
based NoC routers. It tries to maximize the communication performance while ensuring …

The design of scalable and reliable interconnection networks for multicore chips (NoCs)
introduces new design constraints like power consumption, area, and ultra low latencies …

The high-performance computing domain is enriching with the inclusion of Networks-on-chip
(NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the …

An efficient routing algorithm is important for large on-chip networks [network-on-chip (NoC)]
to provide the required communication performance to applications. Implementing NoC …

4 technique for the synthesis of asynchronous sequential circuits from a Signal Transition
Graph(STCJ) specification is clescribed. We give algorithms for synthesis and hazard …