Predictive caching system and method based on memory access which previously followed a cache miss
G Kedem, T Alexander - US Patent 5,778,436, 1998 - Google Patents
Predictive cache memory systems and methods are responsive to cache misses to prefetch
a data block from main memory based upon the data block which last followed the memory …
a data block from main memory based upon the data block which last followed the memory …
Stack management unit and method for a processor having a stack
M Tremblay, JM O'connor - US Patent 6,038,643, 2000 - Google Patents
The present invention provides a stack management unit including a stack cache to
accelerate data transfers between the stack-based computing system and the stack. In one …
accelerate data transfers between the stack-based computing system and the stack. In one …
Address pipelined stack caching method
S Koppala - US Patent 6,289,418, 2001 - Google Patents
The present invention uses a stack management unit includ ing a stack cache to accelerate
data retrieval from a stack and data storage into the stack. In one embodiment, the stack …
data retrieval from a stack and data storage into the stack. In one embodiment, the stack …
Stack caching circuit with overflow/underflow unit
S Koppala - US Patent 6,167,488, 2000 - Google Patents
The present invention provides a Stack management unit including a Stack cache to
accelerate data retrieval from a Stack and data Storage into the Stack. In one embodiment …
accelerate data retrieval from a Stack and data Storage into the Stack. In one embodiment …
Pipelined stack caching circuit
S Koppala - US Patent 6,009,499, 1999 - Google Patents
A stack management unit includes a stack cache to accelerate data retrieval from a stack
and data storage into the stack. The stack management unit also includes an address …
and data storage into the stack. The stack management unit also includes an address …
Multi-stack memory architecture
M Tremblay, JM O'connor - US Patent 6,138,210, 2000 - Google Patents
The present invention provides a unique multi stack memory system to provide access to
multiple portions of the method frames of a stack based computing system. In one …
multiple portions of the method frames of a stack based computing system. In one …
Reissue logic for individually reissuing instructions trapped in a multiissue stack based computing system
S Koppala, RR Buchamwandla - US Patent 6,108,768, 2000 - Google Patents
Single instruction group during a single processing cycle is provided. The execution unit
handles problem causing instruction groups by trapping the problem causing instruc tion …
handles problem causing instruction groups by trapping the problem causing instruc tion …
Length decoder for variable length data
S Koppala, RR Buchamwandla - US Patent 6,170,050, 2001 - Google Patents
A length decoder that rapidly calculates the group lengths of groups of variable length data
words is provided. In accordance with one embodiment, a length decoder includes a length …
words is provided. In accordance with one embodiment, a length decoder includes a length …
Stack caching method with overflow/underflow control using pointers
S Koppala - US Patent 6,131,144, 2000 - Google Patents
The present invention uses a Stack management unit includ ing a Stack cache to accelerate
data retrieval from a Stack and data Storage into the Stack. In one embodiment, the Stack …
data retrieval from a Stack and data Storage into the Stack. In one embodiment, the Stack …
Stack cache miss handling
S Koppala, RR Buchamwandla - US Patent 6,275,903, 2001 - Google Patents
An instruction pipeline is provided Which can handle stack cache misses Without stalling.
The instruction pipeline includes a stack cache fetch stage con? gured to retrieve data from …
The instruction pipeline includes a stack cache fetch stage con? gured to retrieve data from …