Toward smart embedded systems: A self-aware system-on-chip (soc) perspective

N Dutt, A Jantsch, S Sarma - ACM Transactions on Embedded …, 2016 - dl.acm.org
Embedded systems must address a multitude of potentially conflicting design constraints
such as resiliency, energy, heat, cost, performance, security, etc., all in the face of highly …

Full-automatic recognition of various parking slot markings using a hierarchical tree structure

JK Suhr, HG Jung - Optical Engineering, 2013 - spiedigitallibrary.org
A full-automatic method for recognizing parking slot markings is proposed. The proposed
method recognizes various types of parking slot markings by modeling them as a …

Scalable FPGA refurbishment using netlist-driven evolutionary algorithms

RA Ashraf, RF DeMara - IEEE Transactions on Computers, 2013 - ieeexplore.ieee.org
In this work, Field-Programmable Gate Array (FPGA) reconfigurability is exploited to realize
autonomous fault recovery in mission-critical applications at runtime. The proposed Netlist …

Fault-tolerant multiplier using self-healing technique

RK Sakali, NM Sk - Microelectronics Reliability, 2024 - Elsevier
Abstract A Field Programmable Gate Array (FPGA) is a versatile device capable of
reconfiguring the logic of circuits as required. FPGAs are widely utilized in developing critical …

[PDF][PDF] Case Study: Design and Assessment of an Enhanced Geographic Information System for Exploration of Multivariate Health Statistics.

RM Edsall, AM MacEachren, L Pickle - infovis, 2001 - researchgate.net
An implementation of an interactive parallel coordinate plot linked with the ArcView®
geographic information system (GIS) is presented. The integrated geographic visualization …

Hybrid Evolvable Hardware for automatic generation of image filters

MA Almeida, EC Pedrino - Integrated Computer-Aided …, 2018 - content.iospress.com
In this article, a new framework is proposed and implemented for automatic generation of
image filters in reconfigurable hardware (FPGA), called H-EHW (Hybrid-Evolvable …

Resurrecting FPGA intrinsic analog evolvable hardware

D Whitley, J Yoder, N Carpenter - Artificial Life Conference …, 2021 - direct.mit.edu
In the spirit of past century evolvable hardware, we explore the application of evolutionary
algorithms to field programmable gate arrays and provide an open-source platform for …

[图书][B] Design and Architectures for Digital Signal Processing

G Ruiz, JA Michell - 2013 - books.google.com
Digital signal processing (DSP) covers a wide range of applications in which the
implementation of high-performance systems to meet stringent requirements and …

Performance analysis of intrinsic embedded evolvable hardware using memetic and genetic algorithms

R Chandrasekharan… - International Journal of …, 2020 - inderscienceonline.com
This paper discusses the performance analysis of memetic and genetic algorithms (GA and
MA) as the optimising strategy for the design of embedded evolvable hardware. The …

[引用][C] 可演化组合逻辑数字电路的静电放电抗扰特性

满梦华, 刘尚合, 常小龙, 巨政权, 褚杰 - 高电压技术, 2012