Study and analysis of advanced 3D multi-gate junctionless transistors
As the IC technology is evolving very rapidly, the feature size of the device has been
migrating to sub-nanometre regime for achieving the high packing density. To continue with …
migrating to sub-nanometre regime for achieving the high packing density. To continue with …
Simulation of capacitorless DRAM based on the polycrystalline silicon nanotube structure with multiple grain boundaries
In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM),
based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is …
based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is …
A threshold voltage model of silicon-nanotube-based ultrathin double gate-all-around (DGAA) MOSFETs incorporating quantum confinement effects
In this paper, a quantum-mechanical threshold voltage model for ultrathin double gate-all-
around DGAA MOSFETs has been developed by solving three-dimensional (3-D) Poisson's …
around DGAA MOSFETs has been developed by solving three-dimensional (3-D) Poisson's …
Hetro-dielectric (HD) oxide-engineered Junctionless double gate all around (DGAA) nanotube field effect transistor (FET)
Abstract This paper proposed Hetero-Dielectric (HD) Oxide-Engineered Junctionless double
gate all around nanotube (DGAA-NT) FET for performance enhancement in low power …
gate all around nanotube (DGAA-NT) FET for performance enhancement in low power …
Design of capacitorless DRAM based on polycrystalline silicon nanotube structure
In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM)
based on a polycrystalline silicon nanotube structure with a grain boundary (GB) is designed …
based on a polycrystalline silicon nanotube structure with a grain boundary (GB) is designed …
Analytical modeling of subthreshold characteristics of ultra-thin double gate-all-around (DGAA) MOSFETs incorporating quantum confinement effects
In this work, analytical models of subthreshold current and subthreshold swing of short
channel ultra-thin double gate-all-around (DGAA) MOSFETs including quantum confinement …
channel ultra-thin double gate-all-around (DGAA) MOSFETs including quantum confinement …
Negative capacitance silicon nanotube FET: a subthreshold modeling exploration of sub-60 mV/decade swing, negative drain-induced barrier lowering, and threshold …
In this paper, the analytical modeling of surface potential, threshold voltage, subthreshold
swing, and drain-induced barrier lowering (DIBL) of negative capacitance (NC) silicon …
swing, and drain-induced barrier lowering (DIBL) of negative capacitance (NC) silicon …
Sensitivity analysis of silicon nanotube FET (Si NTFET) with TCAD assisted machine learning
In this paper, a multivariable non-linear regression is used to predict the influence of key
device parameters core radius (tc) and channel length (L) on device performance of silicon …
device parameters core radius (tc) and channel length (L) on device performance of silicon …
Modeling of inner-outer gates and temperature dependent gate-induced drain leakage current of junctionless double-gate-all-around FET
In this paper, the temperature-dependent gate-induced drain leakage (GIDL) current model
is proposed with the help of a lateral electric field (EL) across the inner and outer gate …
is proposed with the help of a lateral electric field (EL) across the inner and outer gate …
Machine learning based device simulation using multi-variable non-linear regression to assess the impact of device parameter variability on threshold voltage of …
For the first time, the machine learning approach is proposed for the analysis of device
parameter variability impact on the threshold voltage of silicon-nanotube-based double gate …
parameter variability impact on the threshold voltage of silicon-nanotube-based double gate …