This paper is based on the OR logic operation's small discharging current and transmission
time delay dynamic logic circuit configuration method. In terms of static logic circuits, it …

Subthreshold leakage current becomes the major component of total power dissipation as
scaling down the feature size. In this paper, two new circuit techniques are proposed for …

Background: Main concern in efficient VLSI circuit designing is low-power consumption, high-
speed and noise tolerance capability. Objective: In this paper, two efficient and high …

In recent years, wide fan-in OR logic domino circuits have become essential parts to
implement resister files, PLA, L1 latches, superscalar microprocessors, wide Mux/De-Mux …

Calculating power and delay in VLSI circuits are two main challenges in designing CMOS
VLSI circuits. The manuscript proposes a lector technique-based foot-driven stack transistor …

Leakage power and propagation delay are two significant issues found in sub-micron
technology-based Complementary Metal-Oxide-Semiconductor (CMOS)-based Very Large …

The current technologies are moving towards small size, high speed, and cost-effective
computing systems. The demand of efficient devices such as operating at high speed and …

A circuit with less power consumption, the minimum amount of leakage, and least possible
delay are the primary aim of the circuit designer. In this paper, a circuit exhibiting similar …

Power dissipation, delay and power delay product (PDP) are the major design metrics that
IC designers have to take care of in any logic circuit design. In this paper an energy efficient …