Dual- Independent-Gate FinFETs for Low Power Logic Circuits

M Rostami, K Mohanram - IEEE Transactions on Computer …, 2011 - ieeexplore.ieee.org
This paper describes the electrode work-function, oxide thickness, gate-source/drain
underlap, and silicon thick ness optimization required to realize dual-V th independent-gate …

Low-power multiplexer designs using three-independent-gate field effect transistors

E Giacomin, JR Gonzalez… - 2017 IEEE/ACM …, 2017 - ieeexplore.ieee.org
Three-Independent-Gate Field Effect Transistors (TIGFETs) are capable of different modes of
operation thanks to their additional gate terminals. By electrically controlling their side gates …

[PDF][PDF] Design of high-performance digital logic circuits based on FinFET technology

V Narendar, S Rai, RA Mishra - International Journal of …, 2012 - researchgate.net
Double-gate FinFET is a novel device structure used in the nanometer regime, whereas the
conventional CMOS technology's performance deteriorates due to increased short channel …

Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology

AN Bhoj, NK Jha - 2011 12th International Symposium on …, 2011 - ieeexplore.ieee.org
Multi-gate CMOS devices promise to usher an era of transistors with good electrostatic
integrity at the sub-22nm nodes, which makes it essential to rethink traditional approaches to …

Optimization of dual-threshold independent-gate FinFETs for compact low power logic circuits

X Zhang, J Hu, X Luo - 2016 IEEE 16th International …, 2016 - ieeexplore.ieee.org
This paper proposes the realization of dual-threshold independent-gate FinFETs by
optimizing the FinFET process parameters including the electrode work function, silicon …

Leakage and delay analysis in FinFET array multiplier circuits

J Whitehouse, E John - 2014 IEEE 57th International Midwest …, 2014 - ieeexplore.ieee.org
This paper investigates the performance of array multipliers utilizing FinFET models for the
following feature sizes: 20nm, 16nm, 14nm, 10nm and 7nm. Using basic array multiplier …

Ultracompact and low-power logic circuits via workfunction engineering

TF Canan, S Kaya, A Karanth… - IEEE Journal on …, 2019 - ieeexplore.ieee.org
An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates
based on recently proposed gate workfunction engineering (WFE) approach is provided …

Low leakage and highly noise immune FinFET-based wide fan-in dynamic logic design

V Mahor, M Pattanaik - Journal of Circuits, Systems and Computers, 2015 - World Scientific
Wide fan-in dynamic logic OR gate has always been an integral part of high speed
microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always …

Comprehensive Optimization of Dual Threshold Independent‐Gate FinFET and SRAM Cells

H Ni, J Hu, H Yang, H Zhu - Active and Passive Electronic …, 2018 - Wiley Online Library
Independent‐Gate (IG) FinFET is a promising device in circuit applications due to its two
separated gates, which can be used independently. In this paper, we proposed a …

E-CARES research project: Understanding complex legacy telecommunication systems

A Marburger, D Herzberg - Proceedings Fifth European …, 2001 - ieeexplore.ieee.org
There are many reasons for reverse engineering or re-engineering legacy systems. To date,
many approaches concerning the re-engineering of legacy systems have been made. The …