A device-to-system perspective regarding self-heating enhanced hot carrier degradation in modern field-effect transistors: A topical review
As foreseen by Keyes in the late 1960s, the self-heating effect has emerged as an important
concern for device performance, output power density, run-time variability, and reliability of …
concern for device performance, output power density, run-time variability, and reliability of …
The past and future of multi-gate field-effect transistors: Process challenges and reliability issues
Y Sun, X Yu, R Zhang, B Chen… - Journal of …, 2021 - iopscience.iop.org
This work reviews the state-of-the art multi-gate field-effect transistor (MuGFET) process
technologies and compares the device performance and reliability characteristics of the …
technologies and compares the device performance and reliability characteristics of the …
Investigation of self-heating effects in vertically stacked GAA MOSFET with wrap-around contact
A contact resistance () becomes a major parasitic resistance in highly scaled modern
semiconductor devices. A wrap-around contact (WAC) has been suggested as a promising …
semiconductor devices. A wrap-around contact (WAC) has been suggested as a promising …
A 10 nm FinFET 128 Mb SRAM with assist adjustment system for power, performance, and area optimization
Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology. A 0.040
6T SRAM bitcell is designed for high density (HD), and 0.049 for high performance (HP). The …
6T SRAM bitcell is designed for high density (HD), and 0.049 for high performance (HP). The …
Layout design correlated with self-heating effect in stacked nanosheet transistors
L Cai, W Chen, G Du, X Zhang… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
With technology node scaling down to 5 nm, the narrow device geometry confines the
material thermal conductivity and further aggravates the self-heating effect in gate-all-around …
material thermal conductivity and further aggravates the self-heating effect in gate-all-around …
Evaluation of 10-nm bulk FinFET RF performance—Conventional versus NC-FinFET
In this letter, we have investigated the RF performance of a negative capacitance FinFET
(NC-FinFET) using BSIM-CMG compact model extracted from DC and RF measured data of …
(NC-FinFET) using BSIM-CMG compact model extracted from DC and RF measured data of …
Modeling of effective thermal resistance in sub-14-nm stacked nanowire and FinFETs
In advanced technology nodes, an increase in power density, use of nonplanar
architectures, and novel materials can aggravate local self-heating due to active power …
architectures, and novel materials can aggravate local self-heating due to active power …
Impact of self-heating effect on transistor characterization and reliability issues in sub-10 nm technology nodes
FinFET and fully depleted silicon-on-insulator (FDSOI) structures could further improve
transistor's performance and, however, also introduce some new problems, especially the …
transistor's performance and, however, also introduce some new problems, especially the …
Self-heating and electrothermal properties of advanced sub-5-nm node nanoplate FET
I Myeong, I Song, MJ Kang… - IEEE Electron Device …, 2020 - ieeexplore.ieee.org
In this paper, Self-Heating Effect (SHE) of Gate-All-Around (GAA) nanoplate field effect
transistor (FET) with variations of active area specifications including number of vertically …
transistor (FET) with variations of active area specifications including number of vertically …
Analysis of self heating effect in DC/AC mode in multi-channel GAA-field effect transistor
I Myeong, D Son, H Kim, H Shin - IEEE transactions on electron …, 2019 - ieeexplore.ieee.org
In this article, the self-heating effect (SHE) of both dc and ac for a three-channel nanowire-
field effect transistor (FET) is investigated and analyzed. In the dc mode, as (definition: K) …
field effect transistor (FET) is investigated and analyzed. In the dc mode, as (definition: K) …