Static-timing analysis (STA) has been one of the most pervasive and successful analysis
engines in the design of digital circuits for the last 20 years. However, in recent years, the …

Discrete statistical static timing analysis (SSTA) performs the timing analysis by using
statistical maximum and convolution operations. The maximum is basically a non-linear …

For nanometer manufacturing, process variation causes significant uncertainty for circuit
performance verification. Statistical static timing analysis (SSTA) is thus developed to …

(57) ABSTRACT A method is described for simulating the f-sigma timing path delay of an
integrated circuit design when local transistor variations determine the stochastic delay. This …

For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in
transistor Vt contribute stochastic variation in logic delay that is a large percentage of the …

This paper investigates the residue arithmetic as a solution for the design of variation-
tolerant circuits. Motivated by the modular organization of residue processors, we …

To improve the accuracy of static timing analysis, the traditional nonlinear delay models are
increasingly replaced by more physical gate models, such as current source models and …

Discrete gate sizing and threshold assignment are commonly used tools for optimizing
digital circuits, and ideal methods for incremental optimization. The gate widths and …

As CMOS technology scales down, process variation introduces significant uncertainty in
power and performance to VLSI circuits and significantly affects their reliability. If this …

Systems and methods for determining a chip yield are dis closed. One system includes a first
level integration solver and a second level integration solver. The first level integra tion …