Dielectric breakdown is a sudden and catastrophic increase in the conductivity of an
insulator caused by electrical stress. It is one of the major reliability issues in electronic …

The aim of this review paper is to describe the impact of so-called border traps (BTs) in high-
k gate oxides on the operation and reliability of high-mobility channel transistors. First, a …

We apply a systematic approach to identify a high-k/metal gate stack degradation
mechanism. Our results demonstrate that the SiO 2 interfacial layer controls the overall …

Understanding the degradation dynamics and the breakdown sequence of a bilayer high-k
(HK) gate dielectric stack is crucial for the improvement of device reliability. We present a …

Multifrequency charge-pumping (MFCP) experiments have been used by many groups to
profile the locations and the energy levels of bulk traps within high-kappa gate dielectric …

SiO_2/high-κ dielectric stack is a candidate for replacing the conventional SiO_2-based
dielectric stacks for future Flash memory cells. Electron traps in the high-κ layer can limit the …

The DCIV method was applied to investigate negative bias temperature instability (NBTI) in
SiO2 gate oxides. The DCIV technique, which measures the interface defect density …

The deep depletion behaviors at the structure of Si/SiO 2 with various equivalent oxide
thicknesses (EOTs) are comprehensively studied by magnified capacitance versus gate …

Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric
material (silicon doped hafnium oxide) were studied within the scope of the present work …

The authors study the statistical properties of individual defects in n-type metal-oxide-
semiconductor field-effect transistors (nMOSFETs) using time dependent defect …