Survey of low-power testing of VLSI circuits
P Girard - IEEE Design & test of computers, 2002 - ieeexplore.ieee.org
The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a
discussion of power consumption that gives reasons for and consequences of increased …
discussion of power consumption that gives reasons for and consequences of increased …
[图书][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
Adapting scan architectures for low power operation
L Whetsel - … International Test Conference 2000 (IEEE Cat. No …, 2000 - ieeexplore.ieee.org
Scan architectures are commonly used to test digital circuitry in integrated circuits. This
paper describes a method of adapting conventional scan architectures such that they …
paper describes a method of adapting conventional scan architectures such that they …
A modified clock scheme for a low power BIST test pattern generator
P Girard, L Guiller, C Landrault… - … 19th IEEE VLSI Test …, 2001 - ieeexplore.ieee.org
In this paper, we present a new low power test-per-clock BIST test pattern generator that
provides test vectors which can reduce the switching activity during test operation. The …
provides test vectors which can reduce the switching activity during test operation. The …
Low-transition test pattern generation for BIST-based applications
M Nourani, M Tehranipoor… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
A low transition test pattern generator, called LT-LFSR, is proposed to reduce the average
and peak power of a circuit during test by reducing the transitions among patterns …
and peak power of a circuit during test by reducing the transitions among patterns …
[图书][B] Power-constrained testing of VLSI circuits
N Nicolici, B Al-Hashimi - 2003 - Springer
Increased levels of chip integration combined with physical limitations of heat removal
devices, cooling mechanisms and battery capacity, have established energy-efficiency as an …
devices, cooling mechanisms and battery capacity, have established energy-efficiency as an …
Test pattern generation using thermometer code counter in TPC technique for BIST implementation
This paper introduces a newly pattern generation with Test-Per-Clock technique for Built-In-
Self-Test implementation. This proposed test vector generation generates Multiple Single …
Self-Test implementation. This proposed test vector generation generates Multiple Single …
Low transition LFSR for BIST-based applications
M Tehranipoor, M Nourani… - 14th Asian Test …, 2005 - ieeexplore.ieee.org
This paper presents a low transition test pattern generator, called LT-LFSR, to reduce
average and peak power of a circuit during test by reducing the transitions within randomtest …
average and peak power of a circuit during test by reducing the transitions within randomtest …
Low power pattern generation for BIST architecture
N Ahmed, MH Tehranipour… - 2004 IEEE International …, 2004 - ieeexplore.ieee.org
A new low power test pattern generator using a linear feedback shift register (LFSR), called
LP-TPG, is presented to reduce the average and peak power of a circuit during test. The …
LP-TPG, is presented to reduce the average and peak power of a circuit during test. The …
Test patterns of multiple SIC vectors: Theory and application in BIST schemes
F Liang, L Zhang, S Lei, G Zhang… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our method
generates multiple single-input change (MSIC) vectors in a pattern, ie, each vector applied …
generates multiple single-input change (MSIC) vectors in a pattern, ie, each vector applied …