Recent advances in FPGA reverse engineering
In this paper, we review recent advances in reverse engineering with an emphasis on FPGA
devices and experimentally verified advantages and limitations of reverse engineering tools …
devices and experimentally verified advantages and limitations of reverse engineering tools …
Performance of partial reconfiguration in FPGA systems: A survey and a cost model
Fine-grain reconfigurable devices suffer from the time needed to load the configuration
bitstream. Even for small bitstreams in partially reconfigurable FPGAs this time cannot be …
bitstream. Even for small bitstreams in partially reconfigurable FPGAs this time cannot be …
Moats and drawbridges: An isolation primitive for reconfigurable hardware based systems
T Huffmire, B Brotherton, G Wang… - … IEEE Symposium on …, 2007 - ieeexplore.ieee.org
Blurring the line between software and hardware, reconfigurable devices strike a balance
between the raw high speed of custom silicon and the post-fabrication flexibility of general …
between the raw high speed of custom silicon and the post-fabrication flexibility of general …
Dynamically configurable security for SRAM FPGA bitstreams
FPGAs are becoming increasingly attractive–thanks to the improvement of their capacities
and their performances. Today, FPGAs represent an efficient design solution for numerous …
and their performances. Today, FPGAs represent an efficient design solution for numerous …
Security for volatile FPGAs
S Drimer - 2009 - cl.cam.ac.uk
With reconfigurable devices fast becoming complete systems in their own right, interest in
their security properties has increased. While research on “FPGA security” has been active …
their security properties has increased. While research on “FPGA security” has been active …
DyRACT: A partial reconfiguration enabled accelerator and test platform
Integrating FPGAs with a general purpose computer remains difficult, but recent efforts have
resulted in open frameworks that offer a software API and hardware interface to allow easier …
resulted in open frameworks that offer a software API and hardware interface to allow easier …
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
C Claus, FH Muller, J Zeppenfeld… - 2007 IEEE International …, 2007 - ieeexplore.ieee.org
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time
reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept …
reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept …
Approximated user-perspective rendering in tablet-based augmented reality
M Tomioka, S Ikeda, K Sato - 2013 IEEE International …, 2013 - ieeexplore.ieee.org
This study addresses the problem of geometric consistency between displayed images and
real scenes in augmented reality using a video see-through hand-held display or tablet. To …
real scenes in augmented reality using a video see-through hand-held display or tablet. To …
A protocol for secure remote updates of FPGA configurations
S Drimer, MG Kuhn - International Workshop on Applied Reconfigurable …, 2009 - Springer
We present a security protocol for the remote update of volatile FPGA configurations stored
in non-volatile memory. Our approach can be implemented on existing FPGAs, as it sits …
in non-volatile memory. Our approach can be implemented on existing FPGAs, as it sits …
Using relocatable bitstreams for fault tolerance
DP Montminy, RO Baldwin, PD Williams… - Second NASA/ESA …, 2007 - ieeexplore.ieee.org
The regular structure and addressing scheme for the Virtex-IIfamily of field programmable
gate arrays (FPGAs) allows the relocation of partial bitstreams through direct bitstream …
gate arrays (FPGAs) allows the relocation of partial bitstreams through direct bitstream …