Register allocation is a well-studied problem, but surprisingly little work has been published
on assigning registers for GPU architectures. In this paper we present the register allocator …

GPU's SIMD architecture is a double-edged sword confronting parallel tasks with control
flow divergence. On the one hand, it provides a high performance yet power-efficient …

Models are useful to represent abstractions of software and hardware processes. The Bulk
Synchronous Parallel (BSP) is a bridging model for parallel computation that allows …

Partial control-flow linearization is a code transformation conceived to maximize work
performed in vectorized programs. In this article, we find a new service for it. We show that …

With increasing general purpose programming capability, GPUs have become the mainstay
for a wide variety of compute intensive tasks from cloud to edge computing. Because of its …

Heterogeneous architectures characterize today hardware ranging from super-computers to
smartphones. However, in spite of this importance, programming such systems is still …

Existing state-of-the-art CPU graph frameworks take advantage of multiple cores, but not the
SIMD capability within each core. In this work, we retarget an existing GPU graph algorithm …

Vectorizing compilers employ divergence analysis to detect at which program point a
specific variable is uniform, ie has the same value on all SPMD threads that execute this …

Summary A Graphics Processing Unit (GPU) is a parallel computing coprocessor
specialized in accelerating vector operations. The enormous heterogeneity of parallel …

Nested patterns are one of the most frequently occurring algorithmic themes in GPU
applications where coarse-grained tasks are constituted from a number of fine-grained ones …