Sentiment mining in WebFountain
J Yi, W Niblack - … Conference on Data Engineering (ICDE'05), 2005 - ieeexplore.ieee.org
WebFountain is a platform for very large-scale text analytics applications that allows uniform
access to a wide variety of sources. It enables the deployment of a variety of document-level …
access to a wide variety of sources. It enables the deployment of a variety of document-level …
3D-stacked memory architectures for multi-core processors
GH Loh - ACM SIGARCH computer architecture news, 2008 - dl.acm.org
Three-dimensional integration enables stacking memory directly on top of a microprocessor,
thereby significantly reducing wire delay between the two. Previous studies have examined …
thereby significantly reducing wire delay between the two. Previous studies have examined …
Back to the future: Leveraging Belady's algorithm for improved cache replacement
Belady's algorithm is optimal but infeasible because it requires knowledge of the future. This
paper explains how a cache replacement algorithm can nonetheless learn from Belady's …
paper explains how a cache replacement algorithm can nonetheless learn from Belady's …
A hierarchical neural model of data prefetching
This paper presents Voyager, a novel neural network for data prefetching. Unlike previous
neural models for prefetching, which are limited to learning delta correlations, our model can …
neural models for prefetching, which are limited to learning delta correlations, our model can …
PIPP: Promotion/insertion pseudo-partitioning of multi-core shared caches
Y Xie, GH Loh - ACM SIGARCH Computer Architecture News, 2009 - dl.acm.org
Many multi-core processors employ a large last-level cache (LLC) shared among the
multiple cores. Past research has demonstrated that sharing-oblivious cache management …
multiple cores. Past research has demonstrated that sharing-oblivious cache management …
ChargeCache: Reducing DRAM latency by exploiting row access locality
DRAM latency continues to be a critical bottleneck for system performance. In this work, we
develop a low-cost mechanism, called Charge Cache, that enables faster access to recently …
develop a low-cost mechanism, called Charge Cache, that enables faster access to recently …
SimFlex: statistical sampling of computer system simulation
TF Wenisch, RE Wunderlich, M Ferdman… - IEEE Micro, 2006 - ieeexplore.ieee.org
Timing-accurate full-system multiprocessor simulations can take years because of
architecture and application complexity. Statistical sampling makes simulation-based …
architecture and application complexity. Statistical sampling makes simulation-based …
Linearizing irregular memory accesses for improved correlated prefetching
This paper introduces the Irregular Stream Buffer (ISB), a prefetcher that targets irregular
sequences of temporally correlated memory references. The key idea is to use an extra level …
sequences of temporally correlated memory references. The key idea is to use an extra level …
Specshield: Shielding speculative data from microarchitectural covert channels
Hardware security has recently re-surfaced as a first-order concern to the confidentiality
protections of computing systems. Meltdown and Spectre introduced a new class of …
protections of computing systems. Meltdown and Spectre introduced a new class of …
DRAM refresh mechanisms, penalties, and trade-offs
Ever-growing application data footprints demand faster main memory with larger capacity.
DRAM has been the technology choice for main memory due to its low latency and high …
DRAM has been the technology choice for main memory due to its low latency and high …