This paper presents an approach for generating fault tolerant task mappings of applications,
represented as an application process graph (APG), to a many-core array. The approach …

NoCs (Networks-on-Chip) are an attractive alternative to communication buses for SoCs
(Systems-on-Chip) as they offer both high scalability and low power consumption. However …

The growth in the number of Intellectual Properties (IPs) or the number of cores on the same
chip becomes a critical issue in System-on-Chip (SoC) due to the intra-communication …

In order to be able to handle an arbitrary amount of static communication segment faults in
NoC-based MPSoCs, a flexible fault tolerance mechanism has to be applied. In this …

Feature selection is one of the most important research topics in high dimensional array data
analysis. We propose a two-way filtering based method that utilizes a pair of statistics …

This paper describes an innovation scaling, dependability as became the main problem for
network on chip (NOC). Numerous deficiencies tolerant steering calculations for NOC are …

A fault-tolerant routing algorithm is divided into the following two categories: one is the
building convex fault region surrounding all fault nodes (Fick et al. 2009, Huang et al. 2008 …