A comprehensive review on FinFET in terms of its device structure and performance matrices

MN Reddy, DK Panda - Silicon, 2022 - Springer
The revolutions made in the CMOS technology are brought up by, continuous downscaling
in order to obtain higher density, better performance and low power consumption, causing …

Performance analysis of FinFET based inverter, NAND and NOR circuits at 10 nm, 7 nm and 5 nm node technologies

A Lazzaz, K Bousbahi, M Ghamnia - Facta universitatis-series …, 2023 - doiserbia.nb.rs
Advancement in the semiconductor industry has transformed modern society. A
miniaturization of a silicon transistor is continuing following Moore's empirical law. The …

Performance analysis and optimization of 10 nm TG n-and p-channel SOI FinFETs for circuit applications

A Lazzaz, K Bousbahi… - Facta Universitatis, Series …, 2022 - casopisi.junis.ni.ac.rs
This paper analyses the electrical characteristics of 10 nm tri-gate (TG) N-and P-channel
silicon-on-insulator (SOI) FinFETs with hafnium oxide gate dielectric. The analysis has been …

Optimized mathematical model of experimental characteristics of 14 nm TG N FinFET

A Lazzaz, K Bousbahi, M Ghamnia - Micro and Nanostructures, 2022 - Elsevier
Quantum effects play a dominant role in nanometric structures for which we need to use new
methods to describe this phenomenon in device characterizations. In this paper an …

Comparative analysis of TG FinFET and GAA FinFET in 3 nm technology node

L Abdelaziz, B Khaled… - 2023 27th International …, 2023 - ieeexplore.ieee.org
Leakage current and Short Channel Effects (SCE) are the main barriers in the progress of
FinFET device manufacturing. The miniaturization of the channel length introduces some …

Design, Analysis and Optimization of CMOS Full Adder Based FinFET 10 nm

L Abdelaziz, B Khaled… - 2023 13th International …, 2023 - ieeexplore.ieee.org
The miniaturization of transistors at the Nanometric scale has caused adverse effects on the
performance of devices. Researchers have proposed new structures such as FinFET with …

A New GAA FinFET without n-well or p-well

A Lazzaz, K Bousbahi, M Ghamnia - 2024 - essuir.sumdu.edu.ua
The reduction in size of metal oxide semiconductor (MOS) devices results in the increase of
leakage current due to Quantum effects. The different technologies proposed to overcome …

Impact of the geometric parameters on the performance of silicon TG SOI N FinFET 5nm

K Bousbahi, M Ghamnia - 2022 - researchsquare.com
Semiconductor device dimensions have been downsized to nanoscale dimensions to
upgrade the driving capacity and increasing speed. At the lower technology node, the …