The present invention proposes a Field Programmable Gate Array device comprising a
plurality of con? gurable electri cal connections, a plurality of controlled sWitches, each one …

The present invention concerns a programmable serial interface device. The device
generally comprises a program mable logic device and another die mounted to an assembly …

Structures and techniques are provided for allowing one or more of the following actions to
occur within a Complex Programmable Logic Device (CPLD):(1) Elective use of a fast …

In one aspect, a method of testing an IC is provided. In one embodiment, the method
includes: programming a resistive element in the IC at an intermediate ON state, where in …

Various structures and methods are disclosed related to routing and programming circuitry
on integrated circuits (“IC”) that have arrays of programmable resistive switches. In some …

An array block has at least two sub-array blocks and a first interconnect routing channel
through which a first group of local interconnect lines extend. Each of the two sub-array …

US7139292B1 - Configurable matrix architecture - Google Patents US7139292B1 -
Configurable matrix architecture - Google Patents Configurable matrix architecture …

BACKGROUND A secondary clock network is often used within an inte grated circuit, such
as a programmable logic device (eg, a complex programmable logic device (CPLD) or a …

This application is a division of US application Ser. No. 10/384,276, filed Mar. 6, 2003, now
US Pat. No. 6,809,947 which is a division of US application Ser. No. 09/872,766, filed Jun. 1 …

US8120382B2 - Programmable integrated circuit with mirrored interconnect structure -
Google Patents US8120382B2 - Programmable integrated circuit with mirrored interconnect …