Benchmark figure of merit extensions for low jitter phase locked loops inspired by new PLL architectures
W Bae - IEEE Access, 2022 - ieeexplore.ieee.org
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …
powerful indicator to compare and to normalize performance of different PLL designs …
A 0.2-V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0-dBm output and 5.2-nW sleep power in 28-nm CMOS
This paper reports an ultralow-voltage (ULV) energy-harvesting bluetooth low-energy (BLE)
transmitter (TX). It features: 1) a fully integrated micropower manager (PM) to customize the …
transmitter (TX). It features: 1) a fully integrated micropower manager (PM) to customize the …
All-digital phase locked loop (ADPLL) topologies for RFID system application: A review
An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver
application such as radio-frequency identification (RFID) system has gained popularity by …
application such as radio-frequency identification (RFID) system has gained popularity by …
A Sub-mW Fractional- ADPLL With FOM of −246 dB for IoT Applications
This paper presents a sub-mW fractional-N all-digital phase-locked loop (ADPLL) with
scalable power consumption, which achieves an figure of merit (FOM) of-246 dB. The …
scalable power consumption, which achieves an figure of merit (FOM) of-246 dB. The …
30.5 A 0.5 V BLE transceiver with a 1.9 mW RX achieving− 96.4 dBm sensitivity and 4.1 dB adjacent channel rejection at 1MHz offset in 22nm FDSOI
M Tamura, H Takano, S Shinke, H Fujita… - … Solid-State Circuits …, 2020 - ieeexplore.ieee.org
Towards the emerging AI era, IoT is becoming more important. Current IoT wireless nodes
require replacement or recharging of the battery. This is impractical when a massive number …
require replacement or recharging of the battery. This is impractical when a massive number …
A 0.98 mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of− 246dB for IoT applications in 65nm CMOS
In a world that has become increasingly connected by the Internet, ultra-low-power (ULP)
transceivers (TRX) will be key elements in a variety of short-range network applications. The …
transceivers (TRX) will be key elements in a variety of short-range network applications. The …
A 529-μW fractional-N all-digital PLL using TDC gain auto-calibration and an inverse-class-F DCO in 65-nm CMOS
This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted
fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed …
fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed …
All-digital PLL for Bluetooth low energy using 32.768-kHz reference clock and≤ 0.45-V supply
CC Li, MS Yuan, CC Liao, YT Lin… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
In this paper, we introduce an all-digital phase-locked loop (ADPLL) for Bluetooth low
energy (BLE) that eliminates the need for a crystal oscillator (XO) other than a 32.768-kHz …
energy (BLE) that eliminates the need for a crystal oscillator (XO) other than a 32.768-kHz …
A 0.5-V BLE transceiver with a 1.9-mW RX achieving− 96.4-dBm sensitivity and− 27-dBm tolerance for intermodulation from interferers at 6-and 12-MHz offsets
M Tamura, H Takano, H Nakahara… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
This article presents a 0.5-V RF transceiver fully compliant with Bluetooth low energy (BLE)
standards. The receiver (RX) fabricated in a 22-nm fully depleted silicon on insulator (FD …
standards. The receiver (RX) fabricated in a 22-nm fully depleted silicon on insulator (FD …
A Fractional-N DTC-based ADPLL using path-select multi-delay line TDC and true fractional division technique
Z Jin, A Hu, X Shan, D Liu, C Zhang, J Cui… - Microelectronics Journal, 2024 - Elsevier
This paper presents a fractional-N all-digital phase-locked loop (ADPLL). A 4-bit multi-delay
line time-to-digital converter (MDL-TDC) using path selection technique is proposed to …
line time-to-digital converter (MDL-TDC) using path selection technique is proposed to …