Design and analysis of a heterojunction vertical t-shaped tunnel field effect transistor
In this paper, a heterojunction vertical t-shaped tunnel field effect transistor (V-tTFET) is
proposed, and the scaling issue associated with it is investigated using Sentaurus …
proposed, and the scaling issue associated with it is investigated using Sentaurus …
Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis
In this paper, we investigate the impact of a drain-pocket (DP) adjacent to the drain region in
Tunnel Field-Effect Transistors (TFETs) to effectively suppress the ambipolar current. Using …
Tunnel Field-Effect Transistors (TFETs) to effectively suppress the ambipolar current. Using …
Approach to suppress ambipolar conduction in Tunnel FET using dielectric pocket
The impact of high‐k dielectric pocket (DP) on the ambipolar conduction of tunnel field‐effect
transistors (TFETs) is demonstrated using two‐dimensional Technology Computer Aided …
transistors (TFETs) is demonstrated using two‐dimensional Technology Computer Aided …
Stacked ferroelectric heterojunction tunnel field effect transistor on a buried oxide substrate for enhanced electrical performance
G Gopal, H Garg, H Agrawal… - … Science and Technology, 2022 - iopscience.iop.org
The device behavior of a stacked ferroelectric heterojunction tunnel field effect transistor (Fe-
HTFET) on a buried oxide substrate is investigated in this paper. Si-doped HfO 2 was taken …
HTFET) on a buried oxide substrate is investigated in this paper. Si-doped HfO 2 was taken …
Heterojunction Negative-Capacitance Tunnel-FET as a Promising Candidate for Sub-0.4VVDD Digital Logic Circuits
The objective of this paper is to exemplify the significant improvements achieved in speed
and power-consumption by utilizing negative-capacitance Tunnel FETs in sub-0.4 V DD …
and power-consumption by utilizing negative-capacitance Tunnel FETs in sub-0.4 V DD …
A barrier controlled charge plasma-based TFET with gate engineering for ambipolar suppression and RF/linearity performance improvement
To address the fabrication complexity and cost of nanoscale devices, a dual material control
gate charge-plasma-based tunnel FET (DMCG-CPTFET) is presented for the first time for the …
gate charge-plasma-based tunnel FET (DMCG-CPTFET) is presented for the first time for the …
Impact of pocket layer on linearity and analog/RF performance of InAs-GaSb vertical tunnel field-effect transistor
M Saravanan, E Parthasarathy - Journal of Electronic Materials, 2023 - Springer
In this study, the analog and radio frequency (RF) functionality of an indium arsenide-gallium
antimonide (InAs-GaSb) tunnel field-effect transistor (TFET) with an InAs pocket layer is …
antimonide (InAs-GaSb) tunnel field-effect transistor (TFET) with an InAs pocket layer is …
Simulation study of the double-gate tunnel field-effect transistor with step channel thickness
Double-gate tunnel field-effect transistor (DG TFET) is expected to extend the limitations of
leakage current and subthreshold slope. However, it also suffers from the ambipolar …
leakage current and subthreshold slope. However, it also suffers from the ambipolar …
Improving the scalability of SOI-based tunnel FETs using ground plane in buried oxide
Tunnel field-effect transistors (TFETs) are known to exhibit degraded electrical
characteristics at smaller channel lengths, primarily due to direct source-to-drain band-to …
characteristics at smaller channel lengths, primarily due to direct source-to-drain band-to …
Impact of dielectric pocket on analog and high-frequency performances of cylindrical gate-all-around tunnel FETs
In this paper, a novel structure of cylindrical GAA-TFETs with high-k dielectric pocket is
proposed to improve the analog and high-frequency performances. We have discussed the …
proposed to improve the analog and high-frequency performances. We have discussed the …