Attention mechanisms for object recognition with event-based cameras
Event-based cameras are neuromorphic sensors capable of efficiently encoding visual
information in the form of sparse sequences of events. Being biologically inspired, they are …
information in the form of sparse sequences of events. Being biologically inspired, they are …
PowerTap: All-digital power meter modeling for run-time power monitoring
The power consumption is a key metric to design computing platforms. In particular, the
variety and complexity of current applications fueled an increasing number of run-time …
variety and complexity of current applications fueled an increasing number of run-time …
An efficient network-on-chip router for dataflow architecture
XW Shen, XC Ye, X Tan, D Wang, L Zhang… - Journal of Computer …, 2017 - Springer
Dataflow architecture has shown its advantages in many high-performance computing
cases. In dataflow computing, a large amount of data are frequently transferred among …
cases. In dataflow computing, a large amount of data are frequently transferred among …
DCBuf: a high-performance wireless network-on-chip architecture with distributed wireless interconnects and centralized buffer sharing
C Sun, Y Ouyang, Y Lu - Wireless Networks, 2022 - Springer
Abstract Wireless Network-on-Chips (WiNoCs) were expected to handle the communication
requirements of the long-distance processing elements. Hence, high-performance WiNoC …
requirements of the long-distance processing elements. Hence, high-performance WiNoC …
Hardware and software support for mixed precision computing: a roadmap for embedded and hpc systems
Mixed precision is an approximate computing technique that can be used to trade-off
computation accuracy for performance and/or energy. It can be applied to many error …
computation accuracy for performance and/or energy. It can be applied to many error …
A fresh view on the microarchitectural design of fpga-based risc cpus in the iot era
G Scotti, D Zoni - Journal of Low Power Electronics and Applications, 2019 - mdpi.com
The Internet-of-Things (IoT) revolution has shaped a new application domain where low-
power RISC architectures constitute the standard computational backbone. The current de …
power RISC architectures constitute the standard computational backbone. The current de …
Powerprobe: Run-time power modeling through automatic RTL instrumentation
Online power monitoring represents a de-facto solution to enable energyand power-aware
run-time optimizations for current and future computing architectures. Traditionally, the …
run-time optimizations for current and future computing architectures. Traditionally, the …
Traffic-oriented reconfigurable NoC with augmented inter-port buffer sharing
C Sun, Y Ouyang, H Liang - Frontiers of Information Technology & …, 2024 - Springer
As the number of cores in a multicore system increases, the communication pressure on the
interconnection network also increases. The network-on-chip (NoC) architecture is expected …
interconnection network also increases. The network-on-chip (NoC) architecture is expected …
Predictive resource management for next-generation high-performance computing heterogeneous platforms
Abstract High-Performance Computing (HPC) is rapidly moving towards the adoption of
nodes characterized by an heterogeneous set of processing resources. This has already …
nodes characterized by an heterogeneous set of processing resources. This has already …
A method for correcting characteristic X-ray net peak count from drifted shadow peak
To correct spectral peak drift and obtain more reliable net counts, this study proposes a long
short-term memory (LSTM) model fused with a convolutional neural network (CNN) to …
short-term memory (LSTM) model fused with a convolutional neural network (CNN) to …