A survey of techniques for cache partitioning in multicore processors

S Mittal - ACM Computing Surveys (CSUR), 2017 - dl.acm.org
As the number of on-chip cores and memory demands of applications increase, judicious
management of cache resources has become not merely attractive but imperative. Cache …

The application slowdown model: Quantifying and controlling the impact of inter-application interference at shared caches and main memory

L Subramanian, V Seshadri, A Ghosh, S Khan… - Proceedings of the 48th …, 2015 - dl.acm.org
In a multi-core system, interference at shared resources (such as caches and main memory)
slows down applications running on different cores. Accurately estimating the slowdown of …

High performance and energy-efficient on-chip cache using dual port (1R/1W) spin-orbit torque MRAM

Y Seo, KW Kwon, X Fong, K Roy - IEEE Journal on Emerging …, 2016 - ieeexplore.ieee.org
This paper proposes a dual (1R/1W) port spin-orbit torque magnetic random access memory
(1R/1W SOT-MRAM) for energy efficient on-chip cache applications. Our proposed dual port …

Intelligent fitting global real‐time task scheduling strategy for high‐performance multi‐core systems

J Wu, E Zhao, S Li, Y Wang - CAAI Transactions on Intelligence …, 2022 - Wiley Online Library
With the development of high‐performance computing, it is possible to solve large‐scale
computing problems. However, the irregularity and access characteristics of computing …

A review on shared resource contention in multicores and its mitigating techniques

PN Jain, SK Surve - International Journal of High …, 2020 - inderscienceonline.com
Chip multiprocessor (CMP) systems have become inevitable to meet high computing
demands. In such systems sharing of resources is imperative for better resource utilisation …

Cooperative multi-agent reinforcement learning-based co-optimization of cores, caches, and on-chip network

R Jain, PR Panda, S Subramoney - ACM Transactions on Architecture …, 2017 - dl.acm.org
Modern multi-core systems provide huge computational capabilities, which can be used to
run multiple processes concurrently. To achieve the best possible performance within limited …

GDP: Using dataflow properties to accurately estimate interference-free performance at runtime

M Jahre, L Eeckhout - 2018 IEEE International Symposium on …, 2018 - ieeexplore.ieee.org
Multi-core memory systems commonly share resources between processors. Resource
sharing improves utilization at the cost of increased inter-application interference which may …

LFOC+: A fair OS-level cache-clustering policy for commodity multicore systems

JC Saez, F Castro, G Fanizzi… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Commodity multicore systems are increasingly adopting hardware support that enables the
system software to partition the last-level cache (LLC). This support makes it possible for the …

A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning

R Jain, PR Panda… - Design, Automation & Test …, 2017 - ieeexplore.ieee.org
The widening gap between the processor and memory performance has led to the inclusion
of multiple levels of caches in the modern multi-core systems. Processors with simultaneous …

Premier: A concurrency-aware pseudo-partitioning framework for shared last-level cache

X Lu, R Wang, XH Sun - 2021 IEEE 39th International …, 2021 - ieeexplore.ieee.org
As the number of on-chip cores and application demands increase, efficient management of
shared cache resources becomes imperative. Cache partitioning techniques have been …