Optimum cycle ratio (OCR) algorithms are fundamental to the performance analysis of
(digital or manufacturing) systems with cycles. Some applications in the computer-aided …

VLSI design is probably the most fascinating application area of combinatorial optimization.
Virtually all classical combinatorial optimization problems, and many new ones, occur …

Power dissipation is becoming the most challenging design constraint in nanometer
technologies. Among various design implementation schemes, standard cell ASICs offer the …

Increasingly significant variational effects present a great challenge for delivering desired
clock skew reliably. Non-tree clock network has been recognized as a promising approach …

In deep sub-micron technologies, process variations can cause significant path delay and
clock skew uncertainties thereby lead to timing failure and yield loss. In this paper, we …

With larger chip images and increasingly aggressive technologies, key design processes
must interoperate, PDS, a physical-synthesis system, accomplishes technology closure …

Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's
billion-transistor multichip module, IBM has invested in tools to support its leading-edge …

In this paper we present a new method for clock scheduling and clocktree construction that
improves the performance of high-end ASICs significantly. First, we compute a clock …

The application of general clock skew scheduling is practically limited due to the difficulties
in implementing a wide spectrum of dedicated clock delays in a reliable manner. This results …

(57) ABSTRACT A method is provided that includes: determining a minimum clock cycle that
can be used to propagate a signal about the critical cycle in a circuit design; wherein the …