System and method for designing and optimizing the memory of an embedded processing system
V Gupta - US Patent 7,412,369, 2008 - Google Patents
There is disclosed an apparatus for designing and optimizing a memory for use in an
embedded processing system. The apparatus comprises: 1) a simulation controller for …
embedded processing system. The apparatus comprises: 1) a simulation controller for …
An esl approach for energy consumption analysis of cache memories in soc platforms
The design of complex circuits as SoCs presents two great challenges to designers. One is
the speeding up of system functionality modeling and the second is the implementation of …
the speeding up of system functionality modeling and the second is the implementation of …
Optimizing instruction cache performance of embedded systems
S Bartolini, CA Prete - ACM Transactions on Embedded Computing …, 2005 - dl.acm.org
In the embedded domain, the gap between memory and processor performance and the
increase in application complexity need to be supported without wasting precious system …
increase in application complexity need to be supported without wasting precious system …
Information processing system for measuring the cache effect in a virtual capacity
M Takada, S Nakamura, K Shimada - US Patent 8,332,586, 2012 - Google Patents
The present invention obtains with high precision, in a storage system, the effect of
additional installation or removal of cache memory, that is, the change of the cache hit rate …
additional installation or removal of cache memory, that is, the change of the cache hit rate …
Method and device for determining requirement parameters of at least one physical hardware unit
F Mangold, H Rölle - US Patent 8,457,944, 2013 - Google Patents
In a method and a device for determining requirement parameters of at least one physical
hardware unit, the operating parameters of simulated, virtual hardware units are varied …
hardware unit, the operating parameters of simulated, virtual hardware units are varied …
Method and device for testing a system comprising at least a plurality of software units that can be executed simultaneously
F Mangold, H Rölle - US Patent 8,972,784, 2015 - Google Patents
(57) ABSTRACT A programmable operating time period of at least one soft ware unit is
changed to a settable operating time period. Furthermore, a testing system for validating the …
changed to a settable operating time period. Furthermore, a testing system for validating the …
A methodology for performance predictions of future arm systems modelled in uml
L Pustina, S Schwarzer, P Martini… - 2008 2nd Annual …, 2008 - ieeexplore.ieee.org
The increasing complexity and short product cycles drive developers of mobile systems to
analyse the performance of systems before hardware prototypes are available. Therefore, it …
analyse the performance of systems before hardware prototypes are available. Therefore, it …
Fine-grain design space exploration for a cartographic SoC multiprocessor
Traditionally, in the field of embedded systems low power consumption and low cost have
been always regarded as stringent specification constraints. In recent years, high …
been always regarded as stringent specification constraints. In recent years, high …
A fast procedure placement algorithm for optimal cache use
We present a procedure placement method for embedded applications. We use the trace-
driven simulation to collect information on the use of the cache line and then a heuristic …
driven simulation to collect information on the use of the cache line and then a heuristic …
An environment for energy consumption analysis of cache memories in SoC platforms
The tuning of cache architectures in platforms for embedded systems applications can
dramatically reduce energy consumption. The existing cache exploration environments …
dramatically reduce energy consumption. The existing cache exploration environments …