Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion

A Palchaudhuri, S Sharma, AS Dhar - ACM Transactions on Design …, 2021 - dl.acm.org
Cellular Automata (CA) is attractive for high-speed VLSI implementation due to modularity,
cascadability, and locality of interconnections confined to neighboring logic cells. However …

Fault localization and testability approaches for FPGA fabric aware canonic signed digit recoding implementations

A Palchaudhuri, AS Dhar - Journal of electronic Testing, 2019 - Springer
Canonic signed digit (CSD) recoding finds applications in real time VLSI signal processing.
In this paper, we have proposed optimized FPGA implementations of CSD recoding …

Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs

A Palchaudhuri, AS Dhar - VLSI Design and Test: 21st International …, 2017 - Springer
The ever increasing demand to push the envelope for achieving superlative metrics of VLSI
circuit performance along with denser logic packing and miniaturization of device …