Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges

V Herdt, R Drechsler - Science China Information Sciences, 2022 - Springer
Virtual prototypes (VPs) are crucial in today's design flow. VPs are predominantly created in
SystemC transaction-level modeling (TLM) and are leveraged for early software …

Navigating the landscape for real-time localization and mapping for robotics and virtual and augmented reality

S Saeedi, B Bodin, H Wagstaff, A Nisbet… - Proceedings of the …, 2018 - ieeexplore.ieee.org
Visual understanding of 3-D environments in real time, at low power, is a huge
computational challenge. Often referred to as simultaneous localization and mapping …

[图书][B] Enhanced Virtual Prototyping

RDV Herdt, D Große, R Drechsler - 2021 - Springer
Virtual Prototypes (VPs) play a very important role to cope with the rising complexity in the
design flow of embedded devices. A VP is essentially an executable abstract model of the …

System-level power estimation tool for embedded processor based platforms

SK Rethinagiri, O Palomar, R Ben Atitallah… - Proceedings of the 6th …, 2014 - dl.acm.org
Due to the ever increasing constraints on power consumption in embedded systems, this
paper addresses the need for an efficient power modeling and estimation methodology …

Fast and accurate performance evaluation for RISC-V using virtual prototypes

V Herdt, D Große, R Drechsler - … & Test in Europe Conference & …, 2020 - ieeexplore.ieee.org
RISC-V is gaining huge popularity in particular for embedded systems. Recently, a SystemC-
based Virtual Prototype (VP) has been open sourced to lay the foundation for providing …

Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator

I Böhm, TJK Edler von Koch, SC Kyle, B Franke… - ACM SIGPLAN …, 2011 - dl.acm.org
Dynamic Binary Translation (DBT) is the key technology behind cross-platform virtualization
and allows software compiled for one Instruction Set Architecture (ISA) to be executed on a …

Low overhead dynamic binary translation on arm

A d'Antras, C Gorgovan, J Garside… - Proceedings of the 38th …, 2017 - dl.acm.org
The ARMv8 architecture introduced AArch64, a 64-bit execution mode with a new instruction
set, while retaining binary compatibility with previous versions of the ARM architecture …

AnICA: analyzing inconsistencies in microarchitectural code analyzers

F Ritter, S Hack - Proceedings of the ACM on Programming Languages, 2022 - dl.acm.org
Microarchitectural code analyzers, ie, tools that estimate the throughput of machine code
basic blocks, are important utensils in the tool belt of performance engineers. Recent tools …

Hardware-accelerated cross-architecture full-system virtualization

T Spink, H Wagstaff, B Franke - ACM Transactions on Architecture and …, 2016 - dl.acm.org
Hardware virtualization solutions provide users with benefits ranging from application
isolation through server consolidation to improved disaster recovery and faster server …

Fast cycle estimation methodology for instruction-level emulator

D Thach, Y Tamiya, S Kuwamura… - 2012 Design, Automation …, 2012 - ieeexplore.ieee.org
In this paper, we propose a cycle estimation methodology for fast instruction-level CPU
emulators. This methodology suggests achieving accurate software performance estimation …