This paper presents a modified binary multiplier using Vedic mathematics. The paper
proposes a modification in the previously published Vedic multiplier circuit. The suggested …

In this paper, a new topology for dynamic logic-based full adder is proposed and analyzed.
The XOR and XNOR gates are generally used as basic logic blocks in the full adder design …

Adder is considered the principle unit of every arithmetic and logical operation. Carry select
adder (CSLA) is an adder that helps to speed up operations of several arithmetic function …

Vedic maths based multiplier is a novel and high speed multiplier. Adder is one of the main
components used in this technique. Using fast adder will enhance the overall performance …

The paper presents the HDL implementation of a novel multiplier algorithm based on the
combination of Vedic mathematics and Booth-Wallace tree multiplier. An 8× 8 multiplier is …

This paper proposes a novel method using Vedic mathematics for calculating the square of
binary numbers. An improved Vedic multiplier architecture is used in the binary squaring …

Addition usually affects the overall performance of digital systems and an arithmetic function.
Adders are most widely used in applications like multipliers, DSP (ie, FFT, FIR, and IIR). In …

The first neural network model which was developed for image recognition application
consisted of simple perceptrons. It had input, processing unit, and a single output. Neural …

In this paper, a 128-bit pipeline Adder is presented, in the form of a syntactic Tree Adder by
an introduction of a new modified Carry-Look-Ahead (CLA) that is merged inside the Tree …

A novel method for squaring binary numbers using Vedic mathematics is proposed in this
paper. The implementation of the binary squaring circuit uses the improved Vedic multiplier …