Device and circuit-level assessment of GaSb/Si heterojunction vertical tunnel-FET for low-power applications
This article investigates the performance of a vertically grown GaSb/Si tunnel field effect
transistor (V-TFET) with a source pocket to enhance the performance of the device. The …
transistor (V-TFET) with a source pocket to enhance the performance of the device. The …
Performance assessment of the charge-plasma-based cylindrical GAA vertical nanowire TFET with impact of interface trap charges
N Kumar, A Raman - IEEE Transactions on Electron Devices, 2019 - ieeexplore.ieee.org
In this article, a charge-plasma (CP)-based gate-all-around (GAA) silicon vertical nanowire
tunnel field-effect transistor (NWTFET) is proposed. The effects of interface trap charges …
tunnel field-effect transistor (NWTFET) is proposed. The effects of interface trap charges …
Dual-material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance
To overcome the problem of fabrication complexity and to reducei the cost of microelectronic
devices, a new concept of dual-material control gate with dual-oxide tunnel field-effect …
devices, a new concept of dual-material control gate with dual-oxide tunnel field-effect …
Impact of interface trap charges on analog/RF and linearity performances of dual-material gate-oxide-stack double-gate TFET
This paper investigates the impact of different interface trap charges (ITCs) on dual-material
gate-oxide-stack double-gate TFET (DMGOSDG-TFET) by introducing localized charges …
gate-oxide-stack double-gate TFET (DMGOSDG-TFET) by introducing localized charges …
Interfacial trap charge and self-heating effect based reliability analysis of a Dual-Drain Vertical Tunnel FET
This manuscript exclusively addresses the reliability concern of a double-drain vertical TFET
(DD-VTFET) by analysing the influence of interface trap charges and variation in ambient …
(DD-VTFET) by analysing the influence of interface trap charges and variation in ambient …
III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications
This article presents a comparative study on the performance characteristics of some vertical
tunnel field effect transistor (TFET): conventional all-Si TFET with pocket, In 0.53 Ga 0.47 …
tunnel field effect transistor (TFET): conventional all-Si TFET with pocket, In 0.53 Ga 0.47 …
Performance analysis of heterojunction tunnel FET device with variable temperature
In this paper, the analysis of SiGe source-based heterojunction Tunnel FET device is
reported. The parameters like transconductance (gm), device efficiency (gm/ID), gate-source …
reported. The parameters like transconductance (gm), device efficiency (gm/ID), gate-source …
Effect of interface trap charges on performance variation of heterogeneous gate dielectric junctionless-TFET
In this paper, we investigate the effect of interface trap charges on the variation of
heterogeneous gate dielectric junctionless-tunnel FET (JL-TFET) by introducing both donor …
heterogeneous gate dielectric junctionless-tunnel FET (JL-TFET) by introducing both donor …
Low-K dielectric pocket and workfunction engineering for DC and analog/RF performance improvement in dual material stack gate oxide double gate TFET
Dharmender, K Nigam - Silicon, 2021 - Springer
In this paper, we investigate the effect of low K dielectric pocket on DC and analog/RF
performance in dual material stack gate oxide double gate tunnel field effect transistor. For …
performance in dual material stack gate oxide double gate tunnel field effect transistor. For …
Design and analysis of DGDMJL TFET for biosensing applications
D Manaswi, KS Rao - Silicon, 2023 - Springer
This paper presents a new design of charge plasma junctionless tunnel field effect transistor
(CP JLTFET) with improved ON current, surface potentials. For the ease of fabrication …
(CP JLTFET) with improved ON current, surface potentials. For the ease of fabrication …