[图书][B] Embedded system design: embedded systems foundations of cyber-physical systems, and the internet of things

P Marwedel - 2021 - library.oapen.org
A unique feature of this open access textbook is to provide a comprehensive introduction to
the fundamental knowledge in embedded systems, with applications in cyber-physical …

[PDF][PDF] A survey of different approaches for overcoming the processor-memory bottleneck

D Efnusheva, A Cholakoska, A Tentov - International Journal of …, 2017 - academia.edu
The growing rate of technology improvements has caused dramatic advances in processor
performances, causing significant speed-up of processor working frequency and increased …

[图书][B] Eingebettete Systeme: Grundlagen Eingebetteter Systeme in Cyber-Physikalischen Systemen

P Marwedel - 2021 - library.oapen.org
Abstract Ein Alleinstellungsmerkmal dieses Open-Access-Lehrbuchs ist die umfassende
Einführung in das Grundlagenwissen über eingebettete Systeme mit Anwendungen in cyber …

Exploring data placement in racetrack memory based scratchpad memory

H Mao, C Zhang, G Sun, J Shu - 2015 IEEE Non-Volatile …, 2015 - ieeexplore.ieee.org
Scratchpad Memory (SPM) has been widely adopted in various computing systems to
improve performance of data access. Recently, non-volatile memory technologies (NVMs) …

Scaling datacenter accelerators with compute-reuse architectures

A Fuchs, D Wentzlaff - 2018 ACM/IEEE 45th Annual …, 2018 - ieeexplore.ieee.org
Hardware specialization is commonly used in datacenters to ameliorate the nearing end of
CMOS technology scaling. While offering superior performance and energy-efficiency …

Fast and predictable non-volatile data memory for real-time embedded systems

M Bazzaz, A Hoseinghorban… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Energy consumption and predictability are two important constraints in designing real-time
embedded systems and one of the recently proposed solutions for the energy consumption …

Volatile STT-RAM scratchpad design and data allocation for low energy

G Rodríguez, J Touriño, MT Kandemir - ACM Transactions on …, 2014 - dl.acm.org
On-chip power consumption is one of the fundamental challenges of current technology
scaling. Cache memories consume a sizable part of this power, particularly due to leakage …

STT-RAM buffer design for precision-tunable general-purpose neural network accelerator

L Song, Y Wang, Y Han, H Li… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Multilevel spin toque transfer RAM (STT-RAM) is a suitable storage device for energy-
efficient neural network accelerators (NNAs), which relies on large-capacity on-chip memory …

Reliable and energy efficient MLC STT-RAM buffer for CNN accelerators

M Jasemi, S Hessabi, N Bagherzadeh - Computers & Electrical Engineering, 2020 - Elsevier
We propose a lightweight scheme where the formation of a data block is changed in such a
way that it can tolerate soft errors significantly better than the baseline. The key insight …

Subutai: distributed synchronization primitives in NoC interfaces for legacy parallel-applications

R Cataldo, R Fernandes, KJM Martin… - Proceedings of the 55th …, 2018 - dl.acm.org
Parallel applications are essential for efficiently using the computational power of a
Multiprocessor System-on-Chip (MPSoC). Unfortunately, these applications do not scale …