US5635851A - Read and writable data bus particularly for programmable logic devices - Google
Patents US5635851A - Read and writable data bus particularly for programmable logic devices …

57 ABSTRACT A CMOS output buffer has a first stage with smaller driver transistors and a
second stage having larger driver transis tors. Both stages drive the output in parallel during …

AbuS driver circuit having Slew rate control. According to one embodiment, the bus driver
circuit includes the follow ing elements: a first circuit having an input configured to receive a …

An output circuit which hardly causes ringing etc. in its output waveform even if a high
capacity load is driven at a high speed comprises an input terminal (11), an output terminal …

(*) Notice: Subject to any disclaimer, the term of this $55, A g St. patent is extended or
adjusted under 35 4,464,590 A 8/1984 Rapp USC 154 (b) by 69 days. 4473, 762. A 9/1984 …

Accordingly, the present invention provides, in one form, a low-power inverter for a crystal
oscillator buffer or the like, including an input node for receiving an input signal, an output …

An output buffer with a variable output impedance is described. The buffer is designed so
that the output impedance is set relatively low during the initial portion of the output transition …

A driver for providing binary signals from a data system to a transmission line is disclosed. A
first n-channel transistor has its drain coupled to the transmission line and its source coupled …

[57] ABSTRACT A driver for providing binary signals from a data system to a transmission
line and a method of charging and discharg—ing the driver output transistor is disclosed. A …

A CMOS output buffer has as pull-downs a smaller driver transistor and a larger driver
transistor. Both transistors drive the output low in parallel initially during a voltage transition …