Preesm: A dataflow-based rapid prototyping framework for simplifying multicore dsp programming

M Pelcat, K Desnos, J Heulot, C Guy… - 2014 6th european …, 2014 - ieeexplore.ieee.org
The high performance Digital Signal Processors (DSPs) currently manufactured by Texas
Instruments are heterogeneous multiprocessor architectures. Programming these …

FPGA-based soft-core processors for image processing applications

M Amiri, FM Siddiqui, C Kelly, R Woods… - Journal of signal …, 2017 - Springer
With security and surveillance, there is an increasing need to process image data efficiently
and effectively either at source or in a large data network. Whilst a Field-Programmable Gate …

Power-awarness in coarse-grained reconfigurable multi-functional architectures: a dataflow based strategy

F Palumbo, T Fanni, C Sau, P Meloni - Journal of Signal Processing …, 2017 - Springer
Modern embedded systems, to accommodate different applications or functionalities over
the same substrate and provide flexibility at the hardware level, are often resource …

Reconfigurable coprocessors synthesis in the MPEG-RVC domain

C Sau, L Fanni, P Meloni, L Raffo… - … Computing and FPGAs …, 2015 - ieeexplore.ieee.org
Flexibility and high efficiency are common design drivers in the embedded systems domain.
Coarse-grained reconfigurable coprocessors can tackle these issues, but they suffer of …

Papify: Automatic instrumentation and monitoring of dynamic dataflow applications based on papi

D Madronal, F Arrestier, J Sancho, A Morvan… - IEEE …, 2019 - ieeexplore.ieee.org
The widening of the complexity-productivity gap in application development witnessed in the
last years is becoming an important issue for the developers. New design methods try to …

Partitioning and optimization of high level stream applications for multi clock domain architectures

SC Brunet, E Bezati, C Alberti, M Mattavelli… - SiPS 2013 …, 2013 - ieeexplore.ieee.org
In this paper we propose a design methodology to partition dataflow applications on a multi
clock domain architecture. This work shows how starting from a high level dataflow …

Synthesis and optimization of high-level stream programs

E Bezati, SC Brunet, M Mattavelli… - Proceedings of the …, 2013 - ieeexplore.ieee.org
In this paper we address the problem of translating high-level stream programs, such as
those written in MPEG's RVC-CAL dataflow language, into implementations in …

Methodologies for synthesizing and analyzing dynamic dataflow programs in heterogeneous systems for edge computing

A Bloch, S Casale-Brunet… - IEEE Open Journal of …, 2021 - ieeexplore.ieee.org
The possibility of using the increasing computing power available in cloud infrastructures
requires the development of new approaches for application software development and …

Why comparing system-level MPSoC mapping approaches is difficult: a case study

A Goens, R Khasanov, J Castrillon… - 2016 IEEE 10th …, 2016 - ieeexplore.ieee.org
Software abstractions are crucial to effectively program heterogeneous Multi-Processor
Systems on Chip (MPSoCs). Prime examples of such abstractions are Kahn Process …

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design

C Sau, T Fanni, C Rubattu, L Raffo… - Microprocessors and …, 2021 - Elsevier
Modern embedded and cyber-physical systems require every day more performance, power
efficiency and flexibility, to execute several profiles and functionalities targeting the ever …