In this paper, a high-speed low-power CMOS synchronous up/down counter with a novel
compact toggle flip-flop is proposed to achieve energy-and area-efficient speed …

Flip-flop research in recent years has been motivated by power-and/or energy-efficient
designs. Flip-flop power is based on data activity (DA), which in many applications ranges …

A static contention-free differential flip-flop (SCDFF) is presented in 28-nm CMOS for low-
voltage and low-power applications. The SCDFF offers fully static and contention-free …

In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual
change-sensing scheme is discussed. Further, in order to reduce power consumption, a new …

For a network-on-chip (NoC) with multiple voltage/frequency domains, metastability hurts the
reliability during the clock-domain crossing, especially in the near-threshold-voltage (NTV) …

Conventional low-power flip-flops with reduced or no redundant transitions suffer from
latency increase. To resolve the issue, this article proposes a low-power redundant …

Flip-flops (FFs) are an essential component of digital circuits, yet they use a lot of power and
energy. This paper introduces the VLFF, an extremely low-power flip-flop that operates with …

Conventional high-performance flip-flops suffer from large power consumption at the
nominal supply region and unreliable operation in the low-voltage region. To overcome …

As essential building blocks of sequential digital circuits, optimizing the power consumption
of flip-flops (FFs) can significantly reduce the total energy of digital systems. This paper …

The need for a low-power and high-speed technology for computation of digital signals is
rising due to the fast growth of technological innovations. Flip-flops serve as fundamental …