Computing in memory with spin-transfer torque magnetic RAM

S Jain, A Ranjan, K Roy… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
In-memory computing is a promising approach to addressing the processor-memory data
transfer bottleneck in computing systems. We propose spin-transfer torque compute-in …

Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware

Q Zhu, T Graf, HE Sumbul, L Pileggi… - 2013 IEEE High …, 2013 - ieeexplore.ieee.org
This paper introduces a 3D-stacked logic-in-memory (LiM) system to accelerate the
processing of sparse matrix data that is held in a 3D DRAM system. We build a customized …

A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing

Q Zhu, B Akin, HE Sumbul, F Sadi… - 2013 IEEE …, 2013 - ieeexplore.ieee.org
This paper introduces a 3D-stacked logic-in-memory (LiM) system that integrates the 3D die-
stacked DRAM architecture with the application-specific LiM IC to accelerate important data …

DynaSpAM: Dynamic spatial architecture mapping using out of order instruction schedules

F Liu, H Ahn, SR Beard, T Oh, DI August - Proceedings of the 42nd …, 2015 - dl.acm.org
Spatial architectures are more efficient than traditional Out-of-Order (OOO) processors for
computationally intensive programs. However, spatial architectures require mapping a …

System and method for in-memory computing

S Jain, A Ranjan, K Roy, A Raghunathan - US Patent 10,073,733, 2018 - Google Patents
A memory capable of carrying out compute-in-memory (CiM) operations is disclosed. The
memory includes a matrix of bit cells having a plurality of bit cells along one or more rows …

Computing-in-memory with spintronics

S Jain, S Sapatnekar, JP Wang, K Roy… - … , Automation & Test …, 2018 - ieeexplore.ieee.org
In-memory computing is a promising approach to alleviating the processor-memory data
transfer bottleneck in computing systems. While spintronics has attracted great interest as a …

Pagerank acceleration for large graphs with scalable hardware and two-step spmv

F Sadi, J Sweeney, S McMillan, TM Low… - 2018 IEEE High …, 2018 - ieeexplore.ieee.org
PageRank is an important vertex ranking algorithm that suffers from poor performance and
efficiency due to notorious memory access behavior. Furthermore, when graphs become …

Design and optimization of a stencil engine

JS Brunhaver II - 2015 - search.proquest.com
Application specific processors exploit the structure of algorithms to reduce energy costs and
increase performance. These kinds of optimizations have become more and more important …

Input-aware flow-based computing on memristor crossbars with applications to edge detection

D Chakraborty, S Raj, SL Fernandes… - IEEE Journal on …, 2019 - ieeexplore.ieee.org
Sneak paths in nanoscale memristor crossbars have traditionally been viewed as a problem
in the use of memristor crossbars as non-volatile replacements of traditional volatile RAM …

Understanding the design space of dram-optimized hardware FFT accelerators

B Akın, F Franchetti, JC Hoe - 2014 IEEE 25th International …, 2014 - ieeexplore.ieee.org
As technology scaling is reaching its limits, pointing to the well-known memory and power
wall problems, achieving high-performance and energy-efficient systems is becoming a …