Computing in memory with spin-transfer torque magnetic RAM
In-memory computing is a promising approach to addressing the processor-memory data
transfer bottleneck in computing systems. We propose spin-transfer torque compute-in …
transfer bottleneck in computing systems. We propose spin-transfer torque compute-in …
Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware
This paper introduces a 3D-stacked logic-in-memory (LiM) system to accelerate the
processing of sparse matrix data that is held in a 3D DRAM system. We build a customized …
processing of sparse matrix data that is held in a 3D DRAM system. We build a customized …
A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing
This paper introduces a 3D-stacked logic-in-memory (LiM) system that integrates the 3D die-
stacked DRAM architecture with the application-specific LiM IC to accelerate important data …
stacked DRAM architecture with the application-specific LiM IC to accelerate important data …
DynaSpAM: Dynamic spatial architecture mapping using out of order instruction schedules
Spatial architectures are more efficient than traditional Out-of-Order (OOO) processors for
computationally intensive programs. However, spatial architectures require mapping a …
computationally intensive programs. However, spatial architectures require mapping a …
System and method for in-memory computing
A memory capable of carrying out compute-in-memory (CiM) operations is disclosed. The
memory includes a matrix of bit cells having a plurality of bit cells along one or more rows …
memory includes a matrix of bit cells having a plurality of bit cells along one or more rows …
Computing-in-memory with spintronics
In-memory computing is a promising approach to alleviating the processor-memory data
transfer bottleneck in computing systems. While spintronics has attracted great interest as a …
transfer bottleneck in computing systems. While spintronics has attracted great interest as a …
Pagerank acceleration for large graphs with scalable hardware and two-step spmv
PageRank is an important vertex ranking algorithm that suffers from poor performance and
efficiency due to notorious memory access behavior. Furthermore, when graphs become …
efficiency due to notorious memory access behavior. Furthermore, when graphs become …
Design and optimization of a stencil engine
JS Brunhaver II - 2015 - search.proquest.com
Application specific processors exploit the structure of algorithms to reduce energy costs and
increase performance. These kinds of optimizations have become more and more important …
increase performance. These kinds of optimizations have become more and more important …
Input-aware flow-based computing on memristor crossbars with applications to edge detection
D Chakraborty, S Raj, SL Fernandes… - IEEE Journal on …, 2019 - ieeexplore.ieee.org
Sneak paths in nanoscale memristor crossbars have traditionally been viewed as a problem
in the use of memristor crossbars as non-volatile replacements of traditional volatile RAM …
in the use of memristor crossbars as non-volatile replacements of traditional volatile RAM …
Understanding the design space of dram-optimized hardware FFT accelerators
As technology scaling is reaching its limits, pointing to the well-known memory and power
wall problems, achieving high-performance and energy-efficient systems is becoming a …
wall problems, achieving high-performance and energy-efficient systems is becoming a …