Architectural exploration of the ADRES coarse-grained reconfigurable array

F Bouwens, M Berekovic, A Kanstein… - … : Architectures, Tools and …, 2007 - Springer
Reconfigurable computational architectures are envisioned to deliver power efficient, high
performance, flexible platforms for embedded systems design. The coarse-grained …

Reconfigurable multiprocessor systems: a review

T Dorta, J Jiménez, JL Martin, U Bidarte… - International Journal …, 2010 - Wiley Online Library
Modern digital systems demand increasing electronic resources, so the multiprocessor
platforms are a suitable solution for them. This approach provides better results in terms of …

An FPGA design flow for reconfigurable network-based multi-processor systems on chip

A Kumar, A Hansson, J Huisken… - … Design, Automation & …, 2007 - ieeexplore.ieee.org
Multi-processor systems on chip (MPSoC) platforms are becoming increasingly more
heterogeneous and are shifting towards a more communication-centric methodology …

Overview of fpga-based multiprocessor systems

T Dorta, J Jiménez, JL Martín, U Bidarte… - 2009 International …, 2009 - ieeexplore.ieee.org
Modern Systems-on-Chip (SoC) development is moving toward multiprocessor-based
design. Embedded systems have evolved from an uniprocessor to a multiprocessor …

[PDF][PDF] Інформаційні системи в обліку, аналізі та аудиті

ТО Мороз, ТО Мороз - 2016 - dspace.mnau.edu.ua
Кафедра інформаційних систем і технологій ІНФОРМАЦІЙНІ СИСТЕМИ В ОБ Page 1
МІНІСТЕРСТВО ОСВІТИ І НАУКИ УКРАЇНИ МИКОЛАЇВСЬКИЙ НАЦІОНАЛЬНИЙ АГРАРНИЙ …

rdwired Networks on Chip in FPGAs to Unify Functional and Configuration Interconnects

K Goossens, M Bennebroek, JY Hur… - Second ACM/IEEE …, 2008 - ieeexplore.ieee.org
We propose that networks on chip (NOC) are hardwired in field-programmable gate arrays
(FPGA). Although some area of the FPGA then has a fixed function, this loss of flexibility is …

Definition and SIMD implementation of a multi-processing architecture approach on FPGA

P Bonnot, F Lemonnier, G Edelin, G Gaillat… - Proceedings of the …, 2008 - dl.acm.org
In a context of high performance, low technology access cost and application code
reusability objectives, this paper presents an" architectured FPGA" approach that consists in …

Generic crossbar network on chip for FPGA MPSoCs

D Bafumba-Lokilo, Y Savaria… - 2008 Joint 6th …, 2008 - ieeexplore.ieee.org
Networks-on-chip (NoCs) have emerged as a new design paradigm to implement MPSoCs
that competes with the standard bus approach. They offer more scalability, flexibility, and …

Application specific customization and scalability of soft multiprocessors

D Unnikrishnan, J Zhao… - 2009 17th IEEE …, 2009 - ieeexplore.ieee.org
Although soft microprocessors are widely used in FPGAs, limited work has been performed
regarding how to automatically and efficiently generate soft multiprocessors. In this paper …

High-Level synthesis of loops using the polyhedral model: the MMAlpha software

S Derrien, S Rajopadhye, P Quinton… - High-Level Synthesis: From …, 2008 - Springer
High-level synthesis (HLS) of loops allows efficient handling of intensive computations of an
application, eg in signal processing. Unrolling loops, the classical technique used in most …